TY - GEN
T1 - A single chip 2.5 Gbps CMOS burst mode optical receiver
AU - Chen, Wei-Zen
AU - Gan, Ruei Ming
PY - 2006
Y1 - 2006
N2 - This paper describes the design of a 2.5 Gbps burst-mode optical receiver in a 0.18 μm CMOS process. Integrating both transimpedance amplifier and post limiting amplifier in a single chip, the input sensitivity of the optical receiver is about -18 dBm, and the response time is less than 50 ns. The overall transimpedance gain is 98 dBΩ, and the -3 dB bandwidth is about 1.85 GHz. Operating under a single 1.8 V supply, this chip dissipates only 122 mW.
AB - This paper describes the design of a 2.5 Gbps burst-mode optical receiver in a 0.18 μm CMOS process. Integrating both transimpedance amplifier and post limiting amplifier in a single chip, the input sensitivity of the optical receiver is about -18 dBm, and the response time is less than 50 ns. The overall transimpedance gain is 98 dBΩ, and the -3 dB bandwidth is about 1.85 GHz. Operating under a single 1.8 V supply, this chip dissipates only 122 mW.
UR - http://www.scopus.com/inward/record.url?scp=39749145209&partnerID=8YFLogxK
U2 - 10.1109/VLSIC.2006.1705339
DO - 10.1109/VLSIC.2006.1705339
M3 - Conference contribution
AN - SCOPUS:39749145209
SN - 1424400066
SN - 9781424400065
T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
SP - 120
EP - 121
BT - 2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
T2 - 2006 Symposium on VLSI Circuits, VLSIC
Y2 - 15 June 2006 through 17 June 2006
ER -