A Single-Channel 1.75GS/s, 6-Bit Flash-Assisted SAR ADC with Self-Adaptive Timer and On-Chip Offset Calibration

Yu Sian Liao, Wei Zen Chen

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)


As the data rates of high speed SERDES continue to evolve from tens to hundreds of Gbps, higher order modulation schemes such as pulse amplitude modulation (PAM) or quadrature amplitude modulation (QAM) are widely adopted in wireline communications to boost up the spectral efficiency. Additionally, digital signal processing (DSP) based transceivers become the main stream to cope with the channel non-idealities, such as frequency dependent channel loss, cross talk, and signal reflections. High speed ADCs running at tens of GS/s are demanding at the receiver front-end and play a key role in those applications. Among them, time interleaved successive approximation register (TI-SAR) ADCs are commonly employed thanks to its digitally intensive implementation and performance improvement along with technology scaling. Limited by the sampling rate of each sub-ADC, a large number of TI-ADC banks would complicate the clock tree distribution and timing skew calibration efforts, which would lead to a higher power consumption. [1] demonstrates a flash-assisted (FA) TI-SAR structure can be utilized to enhance the conversion speed with excellent power efficiency. In this paper, a single-channel 1.75 GS/s 6-bit SAR ADC is proposed. It is designed to support 112 Gbps (56 GBaud) PAM-4 receiver through 32X TI implementation. In the DSP based receiver, the ADC output feeds into the FFE for channel equalization. Meanwhile, the ADC output is applied to clock and data recovery (CDR) circuit to generate the global sampling clock. A long latency in the TI-SAR would degrade the CDR jitter tracking capability. To circumvent the design challenges, conventional SERDES receiver AFE requires dual feedback paths. The main loop of CDR is implemented with a short latency, while the ADC loop performs as an auxiliary path for sampling phase adjustment. As the phase detector for a PAM-4 CDR inherently consists of a 2-bit quantizer, to avoid hardware redundancy and reduce system power consumption, this paper proposes a high-speed FA-SAR ADC. In this implementation, the 2 MSBs are generated by flash operation, which can be combined with the PD in CDR to accelerate phase and frequency locking. Meanwhile, it assists the succeeding SAR operation for the remaining bits conversion to avoid noise boosting in the digital FFE.

主出版物標題Proceedings - A-SSCC 2021
主出版物子標題IEEE Asian Solid-State Circuits Conference
發行者Institute of Electrical and Electronics Engineers Inc.
出版狀態Published - 2021
事件2021 IEEE Asian Solid-State Circuits Conference, A-SSCC 2021 - Busan, Korea, Republic of
持續時間: 7 11月 202110 11月 2021


名字Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference


Conference2021 IEEE Asian Solid-State Circuits Conference, A-SSCC 2021
國家/地區Korea, Republic of


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