A Simple Punchthrough Model for Short-Channel MOSFET's

Fu Chieh Hsu; Richard S. Muller; Chen-Ming Hu

doi:10.1109/T-ED.1983.21298

A Simple Punchthrough Model for Short-Channel MOSFET's

Fu Chieh Hsu, Richard S. Muller, Chen-Ming Hu

國際半導體產業學院

研究成果: Article › 同行評審

19 引文斯高帕斯（Scopus）

摘要

Punchthrough currents impose severe limitations on the minimum channel length and leakage currents of scaled MOS transistors. A simple model is proposed to calculate the low-level punchthrough characteristics. Taking into account the two-dimensional geometr cal effects, this model calculates the drain-induced barrier-lowering (DIBL) and the punchthrough current as a function of the processing parameters, and the gate, drain, and substrate bias. Experiments on devices with substrate dopings 6 × 10¹⁴ and 6.6 × 10¹⁵ cm^-3 and channel lengths from 1 to 2 µm show good agreement with the theory.

原文	English
頁（從 - 到）	1354-1359
頁數	6
期刊	IEEE Transactions on Electron Devices
卷	30
發行號	10
DOIs	https://doi.org/10.1109/T-ED.1983.21298
出版狀態	Published - 1 1月 1983

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10.1109/T-ED.1983.21298

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N2 - Punchthrough currents impose severe limitations on the minimum channel length and leakage currents of scaled MOS transistors. A simple model is proposed to calculate the low-level punchthrough characteristics. Taking into account the two-dimensional geometr cal effects, this model calculates the drain-induced barrier-lowering (DIBL) and the punchthrough current as a function of the processing parameters, and the gate, drain, and substrate bias. Experiments on devices with substrate dopings 6 × 1014 and 6.6 × 1015 cm-3 and channel lengths from 1 to 2 µm show good agreement with the theory.

AB - Punchthrough currents impose severe limitations on the minimum channel length and leakage currents of scaled MOS transistors. A simple model is proposed to calculate the low-level punchthrough characteristics. Taking into account the two-dimensional geometr cal effects, this model calculates the drain-induced barrier-lowering (DIBL) and the punchthrough current as a function of the processing parameters, and the gate, drain, and substrate bias. Experiments on devices with substrate dopings 6 × 1014 and 6.6 × 1015 cm-3 and channel lengths from 1 to 2 µm show good agreement with the theory.

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A Simple Punchthrough Model for Short-Channel MOSFET's

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