@inproceedings{588abc9418dd4a26a88f8f4970d8540f,
title = "A simple method for forming sub-30 nm gate patterns with modified I-line double patterning technique",
abstract = "We present a simple modified double-patterning (DP) technique with I-line stepper to define 23 nm nano-scale structures and have successfully fabricated n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with gate length down to 69 nm. With this approach, polycrystalline silicon (poly-Si) gate with line width down to 70 nm could be formed with good control, which far exceeds the resolution limit of conventional I-line lithography.",
keywords = "double pattern, MOSFETs, photoresist ashing",
author = "Tsai, {Tzu I.} and Tien-Sheng Chao and Horng-Chih Lin and Huang, {Tiao Yuan} and Wei, {Yun Jie}",
year = "2011",
month = sep,
day = "26",
doi = "10.1109/INEC.2011.5991710",
language = "English",
isbn = "9781457703799",
series = "Proceedings - International NanoElectronics Conference, INEC",
booktitle = "4th IEEE International NanoElectronics Conference, INEC 2011",
note = "null ; Conference date: 21-06-2011 Through 24-06-2011",
}