A side-channel leakage free coprocessor IC in 0.18μm CMOS for embedded AES-based cryptographic and biometric processing

K. Tiri*, D. Hwang, A. Hodjat, Bo-Cheng Lai, S. Yang, P. Schaumont, I. Verbauwhede

*此作品的通信作者

研究成果: Conference article同行評審

55 引文 斯高帕斯(Scopus)

摘要

Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption and other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC and its design techniques. The IC has been fabricated in 0.18μm CMOS. The coprocessor, which is used for embedded cryptographic and biometric processing, consists of four components: an Advanced Encryption Standard (AES) based cryptographic engine, a fingerprint-matching oracle, a template storage, and an interface unit. Two functionally identical coprocessors have been fabricated on the same die. The first, 'secure', coprocessor is implemented using a logic style called Wave Dynamic Digital Logic (WDDL) and a layout technique called differential routing. The second, 'insecure', coprocessor is implemented using regular standard cells and regular routing techniques. Measurement-based experimental results show that a differential power analysis (DPA) attack on the insecure coprocessor requires only 8,000 acquisitions to disclose the entire 128b secret key. The same attack on the secure coprocessor still does not disclose the entire secret key at 1,500,000 acquisitions. This improvement in DPA resistance of at least 2 orders of magnitude makes the attack de facto infeasible. The required number of measurements is larger than the lifetime of the secret key in most practical systems.

原文English
文章編號14.1
頁(從 - 到)222-227
頁數6
期刊Proceedings - Design Automation Conference
DOIs
出版狀態Published - 2005
事件42nd Design Automation Conference, DAC 2005 - Anaheim, CA, 美國
持續時間: 13 6月 200517 6月 2005

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