A serial link transceiver for USB2 high-speed mode

Shyh-Jye Jou; Shu Hua Kuo; Jui Ta Chiu; Chu King; Chien Hsiung Lee; Tim Liu

doi:10.1109/ISCAS.2001.922172

A serial link transceiver for USB2 high-speed mode

Shyh-Jye Jou, Shu Hua Kuo, Jui Ta Chiu, Chu King, Chien Hsiung Lee, Tim Liu

電子研究所

研究成果: Conference contribution › 同行評審

4 引文斯高帕斯（Scopus）

摘要

The Universal Serial Bus (USB) technology is now becoming an integral part of the personal computer platform. In this paper, the transceiver architecture and circuits are proposed and implemented for USB2 high-speed mode with 480 Mb/s bandwidth. This physical layer of USB2 consists of transmitter, receiver, two envelope detectors and an all-digital clock recovery/data synchronization blocks. It has been implemented with UMC 0.35 /spl mu/m 1P4M 3.3 V CMOS technology and consumes only 156 mW.

原文	English
主出版物標題	ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
頁面	72-75
頁數	4
DOIs	https://doi.org/10.1109/ISCAS.2001.922172
出版狀態	Published - 1 12月 2001
事件	2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 - Sydney, NSW, Australia 持續時間: 6 5月 2001 → 9 5月 2001

出版系列

名字	ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
卷	4

Conference

Conference	2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
國家/地區	Australia
城市	Sydney, NSW
期間	6/05/01 → 9/05/01

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10.1109/ISCAS.2001.922172

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Link to publication in Scopus

引用此

Jou, S-J., Kuo, S. H., Chiu, J. T., King, C., Lee, C. H., & Liu, T. (2001). A serial link transceiver for USB2 high-speed mode. 於 ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings (頁 72-75). [922172] (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; 卷 4). https://doi.org/10.1109/ISCAS.2001.922172

@inproceedings{9f92344d75434f0dbf0a36165a705599,

title = "A serial link transceiver for USB2 high-speed mode",

abstract = "The Universal Serial Bus (USB) technology is now becoming an integral part of the personal computer platform. In this paper, the transceiver architecture and circuits are proposed and implemented for USB2 high-speed mode with 480 Mb/s bandwidth. This physical layer of USB2 consists of transmitter, receiver, two envelope detectors and an all-digital clock recovery/data synchronization blocks. It has been implemented with UMC 0.35 /spl mu/m 1P4M 3.3 V CMOS technology and consumes only 156 mW.",

author = "Shyh-Jye Jou and Kuo, {Shu Hua} and Chiu, {Jui Ta} and Chu King and Lee, {Chien Hsiung} and Tim Liu",

year = "2001",

month = dec,

day = "1",

doi = "10.1109/ISCAS.2001.922172",

language = "English",

isbn = "0780366859",

series = "ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings",

pages = "72--75",

booktitle = "ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings",

note = "2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 ; Conference date: 06-05-2001 Through 09-05-2001",

}

Jou, S-J, Kuo, SH, Chiu, JT, King, C, Lee, CH & Liu, T 2001, A serial link transceiver for USB2 high-speed mode. 於 ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings., 922172, ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings, 卷 4, 頁 72-75, 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001, Sydney, NSW, Australia, 6/05/01. https://doi.org/10.1109/ISCAS.2001.922172

A serial link transceiver for USB2 high-speed mode. / Jou, Shyh-Jye; Kuo, Shu Hua; Chiu, Jui Ta 等.
ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. 2001. p. 72-75 922172 (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; 卷 4).

研究成果: Conference contribution › 同行評審

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T1 - A serial link transceiver for USB2 high-speed mode

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AU - Kuo, Shu Hua

AU - Chiu, Jui Ta

AU - King, Chu

AU - Lee, Chien Hsiung

AU - Liu, Tim

PY - 2001/12/1

Y1 - 2001/12/1

N2 - The Universal Serial Bus (USB) technology is now becoming an integral part of the personal computer platform. In this paper, the transceiver architecture and circuits are proposed and implemented for USB2 high-speed mode with 480 Mb/s bandwidth. This physical layer of USB2 consists of transmitter, receiver, two envelope detectors and an all-digital clock recovery/data synchronization blocks. It has been implemented with UMC 0.35 /spl mu/m 1P4M 3.3 V CMOS technology and consumes only 156 mW.

AB - The Universal Serial Bus (USB) technology is now becoming an integral part of the personal computer platform. In this paper, the transceiver architecture and circuits are proposed and implemented for USB2 high-speed mode with 480 Mb/s bandwidth. This physical layer of USB2 consists of transmitter, receiver, two envelope detectors and an all-digital clock recovery/data synchronization blocks. It has been implemented with UMC 0.35 /spl mu/m 1P4M 3.3 V CMOS technology and consumes only 156 mW.

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U2 - 10.1109/ISCAS.2001.922172

DO - 10.1109/ISCAS.2001.922172

M3 - Conference contribution

AN - SCOPUS:34548501463

SN - 0780366859

SN - 9780780366855

T3 - ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

SP - 72

EP - 75

BT - ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

T2 - 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001

Y2 - 6 May 2001 through 9 May 2001

ER -

A serial link transceiver for USB2 high-speed mode

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