A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics

Ke Wei Su; Yi Ming Sheu; Chung Kai Lin; Sheng Jier Yang; Wen Jya Liang; Xuemei Xi; Chung Shi Chiang; Jaw Kang Her; Yu Tai Chia; Carlos H. Diaz; Chen-Ming Hu

doi:10.1109/CICC.2003.1249396

A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics

Ke Wei Su^*, Yi Ming Sheu, Chung Kai Lin, Sheng Jier Yang, Wen Jya Liang, Xuemei Xi, Chung Shi Chiang, Jaw Kang Her, Yu Tai Chia, Carlos H. Diaz, Chen-Ming Hu

^*此作品的通信作者

國際半導體產業學院

研究成果: Conference article › 同行評審

74 引文斯高帕斯（Scopus）

摘要

This paper demonstrates a new compact and scaleable model about the mechanical stress effect on MOS electrical performance induced by the shallow trench isolation (STI). This model has included the influence of STI stress not only on the mobility and saturation velocity, but also on the threshold voltage and other important second-order effects. Thus it could simulate the layout dependence of MOS performance with good accuracy and efficiency. We have verified this model with various device dimensions and layout styles of our advanced MOS technologies. And it shows the importance of this new model for circuit design in advanced CMOS generations.

原文	English
頁（從 - 到）	245-248
頁數	4
期刊	Proceedings of the Custom Integrated Circuits Conference
DOIs	https://doi.org/10.1109/CICC.2003.1249396
出版狀態	Published - 2003
事件	Proceedings of the IEEE 2003 Custom Integrated Circuits Conference - San Jose, CA, 美國持續時間: 21 9月 2003 → 24 9月 2003

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10.1109/CICC.2003.1249396

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@article{ea0fad8d1ed54a1d955f5f7ea76ff168,

title = "A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics",

abstract = "This paper demonstrates a new compact and scaleable model about the mechanical stress effect on MOS electrical performance induced by the shallow trench isolation (STI). This model has included the influence of STI stress not only on the mobility and saturation velocity, but also on the threshold voltage and other important second-order effects. Thus it could simulate the layout dependence of MOS performance with good accuracy and efficiency. We have verified this model with various device dimensions and layout styles of our advanced MOS technologies. And it shows the importance of this new model for circuit design in advanced CMOS generations.",

author = "Su, {Ke Wei} and Sheu, {Yi Ming} and Lin, {Chung Kai} and Yang, {Sheng Jier} and Liang, {Wen Jya} and Xuemei Xi and Chiang, {Chung Shi} and Her, {Jaw Kang} and Chia, {Yu Tai} and Diaz, {Carlos H.} and Chen-Ming Hu",

year = "2003",

doi = "10.1109/CICC.2003.1249396",

language = "English",

pages = "245--248",

journal = "Proceedings of the Custom Integrated Circuits Conference",

issn = "0886-5930",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the IEEE 2003 Custom Integrated Circuits Conference ; Conference date: 21-09-2003 Through 24-09-2003",

}

TY - JOUR

T1 - A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics

AU - Su, Ke Wei

AU - Sheu, Yi Ming

AU - Lin, Chung Kai

AU - Yang, Sheng Jier

AU - Liang, Wen Jya

AU - Xi, Xuemei

AU - Chiang, Chung Shi

AU - Her, Jaw Kang

AU - Chia, Yu Tai

AU - Diaz, Carlos H.

AU - Hu, Chen-Ming

PY - 2003

Y1 - 2003

N2 - This paper demonstrates a new compact and scaleable model about the mechanical stress effect on MOS electrical performance induced by the shallow trench isolation (STI). This model has included the influence of STI stress not only on the mobility and saturation velocity, but also on the threshold voltage and other important second-order effects. Thus it could simulate the layout dependence of MOS performance with good accuracy and efficiency. We have verified this model with various device dimensions and layout styles of our advanced MOS technologies. And it shows the importance of this new model for circuit design in advanced CMOS generations.

AB - This paper demonstrates a new compact and scaleable model about the mechanical stress effect on MOS electrical performance induced by the shallow trench isolation (STI). This model has included the influence of STI stress not only on the mobility and saturation velocity, but also on the threshold voltage and other important second-order effects. Thus it could simulate the layout dependence of MOS performance with good accuracy and efficiency. We have verified this model with various device dimensions and layout styles of our advanced MOS technologies. And it shows the importance of this new model for circuit design in advanced CMOS generations.

UR - http://www.scopus.com/inward/record.url?scp=0242696135&partnerID=8YFLogxK

U2 - 10.1109/CICC.2003.1249396

DO - 10.1109/CICC.2003.1249396

M3 - Conference article

AN - SCOPUS:0242696135

SN - 0886-5930

SP - 245

EP - 248

JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

T2 - Proceedings of the IEEE 2003 Custom Integrated Circuits Conference

Y2 - 21 September 2003 through 24 September 2003

ER -

A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics

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