A scalable digitalized buffer for gigabit I/O

Hung Wen Lu; Chau-Chin Su; Chien-Nan Liu

doi:10.1109/TCSII.2008.925661

A scalable digitalized buffer for gigabit I/O

Hung Wen Lu^*, Chau-Chin Su, Chien-Nan Liu

^*此作品的通信作者

研究成果: Article › 同行評審

8 引文斯高帕斯（Scopus）

摘要

A serial input-output (I/O) composed of inverters and transmission gates only is proposed to achieve high supply voltage scalability and low area overhead. The inverter with an inductive biasing circuit can extend bandwidth, and reduce the simultaneous switching noise simultaneously. With a TSMC 0.18-μm CMOS process, the I/O occupies an area of 0.014 mm² and operates from 4 Gbps.9 V to 1.5 Gbps.1 V.

原文	American English
頁（從 - 到）	1026-1030
頁數	5
期刊	IEEE Transactions on Circuits and Systems I: Regular Papers
卷	55
發行號	10
DOIs	https://doi.org/10.1109/TCSII.2008.925661
出版狀態	Published - 10月 2008

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A scalable digitalized buffer for gigabit I/O

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