A scalable digitalized buffer for gigabit I/O

HungWen Lu; Chau-Chin Su; Chien-Nan Liu

doi:10.1109/CICC.2008.4672068

A scalable digitalized buffer for gigabit I/O

HungWen Lu^*, Chau-Chin Su, Chien-Nan Liu

^*此作品的通信作者

研究成果: Conference article › 同行評審

1 引文斯高帕斯（Scopus）

摘要

A serial I/O composed of inverters and transmission gates only is proposed to achieve high supply voltage scalability and low area overhead. The inverter with an inductive biasing circuit can extend bandwidth, and reduce the SSN simultaneously. With a TSMC 0.18μm CMOS process, the I/O occupies an area of 0.014mm² and operates from [email protected] to [email protected].

原文	American English
文章編號	4672068
頁（從 - 到）	241-244
頁數	4
期刊	Proceedings of the Custom Integrated Circuits Conference
DOIs	https://doi.org/10.1109/CICC.2008.4672068
出版狀態	Published - 2008
事件	IEEE 2008 Custom Integrated Circuits Conference, CICC 2008 - San Jose, CA, 美國持續時間: 21 9月 2008 → 24 9月 2008

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title = "A scalable digitalized buffer for gigabit I/O",

abstract = "A serial I/O composed of inverters and transmission gates only is proposed to achieve high supply voltage scalability and low area overhead. The inverter with an inductive biasing circuit can extend bandwidth, and reduce the SSN simultaneously. With a TSMC 0.18μm CMOS process, the I/O occupies an area of 0.014mm2 and operates from [email protected] to [email protected].",

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author = "HungWen Lu and Chau-Chin Su and Chien-Nan Liu",

year = "2008",

doi = "10.1109/CICC.2008.4672068",

language = "American English",

pages = "241--244",

journal = "Proceedings of the Custom Integrated Circuits Conference",

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note = "IEEE 2008 Custom Integrated Circuits Conference, CICC 2008 ; Conference date: 21-09-2008 Through 24-09-2008",

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AU - Lu, HungWen

AU - Su, Chau-Chin

AU - Liu, Chien-Nan

PY - 2008

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AB - A serial I/O composed of inverters and transmission gates only is proposed to achieve high supply voltage scalability and low area overhead. The inverter with an inductive biasing circuit can extend bandwidth, and reduce the SSN simultaneously. With a TSMC 0.18μm CMOS process, the I/O occupies an area of 0.014mm2 and operates from [email protected] to [email protected].

KW - Buffer

KW - I/O

KW - SSN

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U2 - 10.1109/CICC.2008.4672068

DO - 10.1109/CICC.2008.4672068

M3 - Conference article

AN - SCOPUS:57849161990

SN - 0886-5930

SP - 241

EP - 244

JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

M1 - 4672068

T2 - IEEE 2008 Custom Integrated Circuits Conference, CICC 2008

Y2 - 21 September 2008 through 24 September 2008

ER -

A scalable digitalized buffer for gigabit I/O

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