A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI

Brian Zimmer; Yunsup Lee; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Ben Keller; Stevo Bailey; Milovan Blagojevic; Pi Feng Chiu; Hanh Phuc Le; Po-Hung Chen; Nicholas Sutardja; Rimas Avizienis; Andrew Waterman; Brian Richards; Philippe Flatresse; Elad Alon; Krste Asanović; Borivoje Nikolić

doi:10.1109/VLSIC.2015.7231305

A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI

Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi Feng Chiu, Hanh Phuc Le, Po-Hung Chen, Nicholas Sutardja, Rimas Avizienis, Andrew Waterman, Brian Richards, Philippe Flatresse, Elad Alon, Krste Asanović, Borivoje Nikolić

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研究成果: Conference contribution › 同行評審

29 引文斯高帕斯（Scopus）

摘要

This work demonstrates a RISC-V vector microprocessor implemented in 28nm FDSOI with fully-integrated non-interleaved switched-capacitor DCDC (SC-DCDC) converters and adaptive clocking that generates four on-chip voltages between 0.5V and 1V using only 1.0V core and 1.8V IO voltage inputs. The design pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices.

原文	English
主出版物標題	2015 Symposium on VLSI Circuits, VLSI Circuits 2015
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	C316-C317
ISBN（電子）	9784863485020
DOIs	https://doi.org/10.1109/VLSIC.2015.7231305
出版狀態	Published - 31 8月 2015
事件	29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015 - Kyoto, Japan 持續時間: 17 6月 2015 → 19 6月 2015

出版系列

名字	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
卷	2015-August

Conference

Conference	29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015
國家/地區	Japan
城市	Kyoto
期間	17/06/15 → 19/06/15

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10.1109/VLSIC.2015.7231305

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Zimmer, B., Lee, Y., Puggelli, A., Kwak, J., Jevtic, R., Keller, B., Bailey, S., Blagojevic, M., Chiu, P. F., Le, H. P., Chen, P-H., Sutardja, N., Avizienis, R., Waterman, A., Richards, B., Flatresse, P., Alon, E., Asanović, K., & Nikolić, B. (2015). A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI. 於 2015 Symposium on VLSI Circuits, VLSI Circuits 2015 (頁 C316-C317). [7231305] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; 卷 2015-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2015.7231305

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title = "A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI",

abstract = "This work demonstrates a RISC-V vector microprocessor implemented in 28nm FDSOI with fully-integrated non-interleaved switched-capacitor DCDC (SC-DCDC) converters and adaptive clocking that generates four on-chip voltages between 0.5V and 1V using only 1.0V core and 1.8V IO voltage inputs. The design pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices.",

author = "Brian Zimmer and Yunsup Lee and Alberto Puggelli and Jaehwa Kwak and Ruzica Jevtic and Ben Keller and Stevo Bailey and Milovan Blagojevic and Chiu, {Pi Feng} and Le, {Hanh Phuc} and Po-Hung Chen and Nicholas Sutardja and Rimas Avizienis and Andrew Waterman and Brian Richards and Philippe Flatresse and Elad Alon and Krste Asanovi{\'c} and Borivoje Nikoli{\'c}",

year = "2015",

month = aug,

day = "31",

doi = "10.1109/VLSIC.2015.7231305",

language = "English",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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Zimmer, B, Lee, Y, Puggelli, A, Kwak, J, Jevtic, R, Keller, B, Bailey, S, Blagojevic, M, Chiu, PF, Le, HP, Chen, P-H, Sutardja, N, Avizienis, R, Waterman, A, Richards, B, Flatresse, P, Alon, E, Asanović, K & Nikolić, B 2015, A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI. 於 2015 Symposium on VLSI Circuits, VLSI Circuits 2015., 7231305, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, 卷 2015-August, Institute of Electrical and Electronics Engineers Inc., 頁 C316-C317, 29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015, Kyoto, Japan, 17/06/15. https://doi.org/10.1109/VLSIC.2015.7231305

A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI. / Zimmer, Brian; Lee, Yunsup; Puggelli, Alberto 等.

2015 Symposium on VLSI Circuits, VLSI Circuits 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. C316-C317 7231305 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; 卷 2015-August).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI

AU - Zimmer, Brian

AU - Lee, Yunsup

AU - Puggelli, Alberto

AU - Kwak, Jaehwa

AU - Jevtic, Ruzica

AU - Keller, Ben

AU - Bailey, Stevo

AU - Blagojevic, Milovan

AU - Chiu, Pi Feng

AU - Le, Hanh Phuc

AU - Chen, Po-Hung

AU - Sutardja, Nicholas

AU - Avizienis, Rimas

AU - Waterman, Andrew

AU - Richards, Brian

AU - Flatresse, Philippe

AU - Alon, Elad

AU - Asanović, Krste

AU - Nikolić, Borivoje

PY - 2015/8/31

Y1 - 2015/8/31

N2 - This work demonstrates a RISC-V vector microprocessor implemented in 28nm FDSOI with fully-integrated non-interleaved switched-capacitor DCDC (SC-DCDC) converters and adaptive clocking that generates four on-chip voltages between 0.5V and 1V using only 1.0V core and 1.8V IO voltage inputs. The design pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices.

AB - This work demonstrates a RISC-V vector microprocessor implemented in 28nm FDSOI with fully-integrated non-interleaved switched-capacitor DCDC (SC-DCDC) converters and adaptive clocking that generates four on-chip voltages between 0.5V and 1V using only 1.0V core and 1.8V IO voltage inputs. The design pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices.

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M3 - Conference contribution

AN - SCOPUS:84957882903

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

SP - C316-C317

BT - 2015 Symposium on VLSI Circuits, VLSI Circuits 2015

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 17 June 2015 through 19 June 2015

ER -

Zimmer B, Lee Y, Puggelli A, Kwak J, Jevtic R, Keller B 等. A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI. 於 2015 Symposium on VLSI Circuits, VLSI Circuits 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. C316-C317. 7231305. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.1109/VLSIC.2015.7231305

A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI

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