A rescheduling and fast pipeline VLSI architecture for lifting-based discrete wavelet transform

Bing-Fei Wu; Chung Fu Lin

doi:10.1109/ISCAS.2003.1206078

A rescheduling and fast pipeline VLSI architecture for lifting-based discrete wavelet transform

Bing-Fei Wu^*, Chung Fu Lin

^*此作品的通信作者

電機工程學系

研究成果: Conference article › 同行評審

22 引文斯高帕斯（Scopus）

摘要

In this paper, we propose a fast pipeline VLSI architecture for 1-D lifting-based discrete wavelet transform (DWT). This design method merges the filtering steps called the predictor and updater into one single step. Based on this modified algorithm, we explore the data dependency of the input and output signals, and thus make the pipeline design more efficiently for hardware implementation under the same processor elements proposed in previous works. Moreover, the inverse DWT case also adopts the same architecture as the forward DWT. Finally, the area and the working frequency of the proposed architecture in 0.35um technology are 2.511x2.510 mm², and 150 MHz, respectively.

原文	English
文章編號	1206078
頁（從 - 到）	732-735
頁數	4
期刊	Proceedings - IEEE International Symposium on Circuits and Systems
卷	2
DOIs	https://doi.org/10.1109/ISCAS.2003.1206078
出版狀態	Published - 25 5月 2003
事件	Proceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, 泰國持續時間: 25 5月 2003 → 28 5月 2003

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10.1109/ISCAS.2003.1206078

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abstract = "In this paper, we propose a fast pipeline VLSI architecture for 1-D lifting-based discrete wavelet transform (DWT). This design method merges the filtering steps called the predictor and updater into one single step. Based on this modified algorithm, we explore the data dependency of the input and output signals, and thus make the pipeline design more efficiently for hardware implementation under the same processor elements proposed in previous works. Moreover, the inverse DWT case also adopts the same architecture as the forward DWT. Finally, the area and the working frequency of the proposed architecture in 0.35um technology are 2.511x2.510 mm2, and 150 MHz, respectively.",

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AU - Wu, Bing-Fei

AU - Lin, Chung Fu

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N2 - In this paper, we propose a fast pipeline VLSI architecture for 1-D lifting-based discrete wavelet transform (DWT). This design method merges the filtering steps called the predictor and updater into one single step. Based on this modified algorithm, we explore the data dependency of the input and output signals, and thus make the pipeline design more efficiently for hardware implementation under the same processor elements proposed in previous works. Moreover, the inverse DWT case also adopts the same architecture as the forward DWT. Finally, the area and the working frequency of the proposed architecture in 0.35um technology are 2.511x2.510 mm2, and 150 MHz, respectively.

AB - In this paper, we propose a fast pipeline VLSI architecture for 1-D lifting-based discrete wavelet transform (DWT). This design method merges the filtering steps called the predictor and updater into one single step. Based on this modified algorithm, we explore the data dependency of the input and output signals, and thus make the pipeline design more efficiently for hardware implementation under the same processor elements proposed in previous works. Moreover, the inverse DWT case also adopts the same architecture as the forward DWT. Finally, the area and the working frequency of the proposed architecture in 0.35um technology are 2.511x2.510 mm2, and 150 MHz, respectively.

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DO - 10.1109/ISCAS.2003.1206078

M3 - Conference article

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JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

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T2 - Proceedings of the 2003 IEEE International Symposium on Circuits and Systems

Y2 - 25 May 2003 through 28 May 2003

ER -

A rescheduling and fast pipeline VLSI architecture for lifting-based discrete wavelet transform

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