A rescheduling and fast pipeline VLSI architecture for lifting-based discrete wavelet transform

Bing-Fei Wu*, Chung Fu Lin

*此作品的通信作者

研究成果: Conference article同行評審

22 引文 斯高帕斯(Scopus)

摘要

In this paper, we propose a fast pipeline VLSI architecture for 1-D lifting-based discrete wavelet transform (DWT). This design method merges the filtering steps called the predictor and updater into one single step. Based on this modified algorithm, we explore the data dependency of the input and output signals, and thus make the pipeline design more efficiently for hardware implementation under the same processor elements proposed in previous works. Moreover, the inverse DWT case also adopts the same architecture as the forward DWT. Finally, the area and the working frequency of the proposed architecture in 0.35um technology are 2.511x2.510 mm2, and 150 MHz, respectively.

原文English
文章編號1206078
頁(從 - 到)732-735
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
2
DOIs
出版狀態Published - 25 5月 2003
事件Proceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand
持續時間: 25 5月 200328 5月 2003

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