A reliable brain computer interface implemented on FPGA for mobile dialing system

Chih Wei Feng; Jui Chung Chang; Wei Chen Chen; Wai-Chi  Fang

doi:10.1109/ICCE-TW.2015.7216805

A reliable brain computer interface implemented on FPGA for mobile dialing system

Chih Wei Feng, Jui Chung Chang, Wei Chen Chen, Wai-Chi Fang

電子研究所

研究成果: Conference contribution › 同行評審

1 引文斯高帕斯（Scopus）

摘要

This paper demonstrates a high performance brain-computer interface (BCI) that allows users to dial phone numbers. The system is based on Canonical Correlation Analysis (CCA) and Steady-State Visual Evoked Potential (SSVEP). Through six buttons (9Hz, 10Hz, 11Hz, 12Hz, 13 Hz, 14Hz) displayed on the screen, subjects can choose the number by gazing at the computer interface. This proposed EEG (Electroencephalography) system has been implemented in Field-Programmable Gate Arrays (FPGA) and it features high accuracy, integration density, and low cost. These features are meaningful for implementing a real time SSVEP-based BCI.

原文	English
主出版物標題	2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	110-111
頁數	2
ISBN（電子）	9781479987443
DOIs	https://doi.org/10.1109/ICCE-TW.2015.7216805
出版狀態	Published - 20 8月 2015
事件	2nd IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015 - Taipei, 台灣持續時間: 6 6月 2015 → 8 6月 2015

出版系列

名字	2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015

Conference

Conference	2nd IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015
國家/地區	台灣
城市	Taipei
期間	6/06/15 → 8/06/15

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10.1109/ICCE-TW.2015.7216805

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Link to publication in Scopus

引用此

Feng, C. W., Chang, J. C., Chen, W. C., & Fang, W.-C. (2015). A reliable brain computer interface implemented on FPGA for mobile dialing system. 於 2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015 (頁 110-111). 文章 7216805 (2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCE-TW.2015.7216805

Feng, Chih Wei ; Chang, Jui Chung ; Chen, Wei Chen 等. / A reliable brain computer interface implemented on FPGA for mobile dialing system. 2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 頁 110-111 (2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015).

@inproceedings{657f199d67234f5999cb0a6d19677774,

title = "A reliable brain computer interface implemented on FPGA for mobile dialing system",

abstract = "This paper demonstrates a high performance brain-computer interface (BCI) that allows users to dial phone numbers. The system is based on Canonical Correlation Analysis (CCA) and Steady-State Visual Evoked Potential (SSVEP). Through six buttons (9Hz, 10Hz, 11Hz, 12Hz, 13 Hz, 14Hz) displayed on the screen, subjects can choose the number by gazing at the computer interface. This proposed EEG (Electroencephalography) system has been implemented in Field-Programmable Gate Arrays (FPGA) and it features high accuracy, integration density, and low cost. These features are meaningful for implementing a real time SSVEP-based BCI.",

keywords = "Accuracy, Bandwidth, Brain-computer interfaces, Correlation, Electroencephalography, Field programmable gate arrays, Visualization",

author = "Feng, {Chih Wei} and Chang, {Jui Chung} and Chen, {Wei Chen} and Wai-Chi Fang",

year = "2015",

month = aug,

day = "20",

doi = "10.1109/ICCE-TW.2015.7216805",

language = "English",

series = "2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "110--111",

booktitle = "2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015",

address = "美國",

note = "2nd IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015 ; Conference date: 06-06-2015 Through 08-06-2015",

}

Feng, CW, Chang, JC, Chen, WC & Fang, W-C 2015, A reliable brain computer interface implemented on FPGA for mobile dialing system. 於 2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015., 7216805, 2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015, Institute of Electrical and Electronics Engineers Inc., 頁 110-111, 2nd IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015, Taipei, 台灣, 6/06/15. https://doi.org/10.1109/ICCE-TW.2015.7216805

A reliable brain computer interface implemented on FPGA for mobile dialing system. / Feng, Chih Wei; Chang, Jui Chung; Chen, Wei Chen 等.
2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 110-111 7216805 (2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - A reliable brain computer interface implemented on FPGA for mobile dialing system

AU - Feng, Chih Wei

AU - Chang, Jui Chung

AU - Chen, Wei Chen

AU - Fang, Wai-Chi

PY - 2015/8/20

Y1 - 2015/8/20

N2 - This paper demonstrates a high performance brain-computer interface (BCI) that allows users to dial phone numbers. The system is based on Canonical Correlation Analysis (CCA) and Steady-State Visual Evoked Potential (SSVEP). Through six buttons (9Hz, 10Hz, 11Hz, 12Hz, 13 Hz, 14Hz) displayed on the screen, subjects can choose the number by gazing at the computer interface. This proposed EEG (Electroencephalography) system has been implemented in Field-Programmable Gate Arrays (FPGA) and it features high accuracy, integration density, and low cost. These features are meaningful for implementing a real time SSVEP-based BCI.

AB - This paper demonstrates a high performance brain-computer interface (BCI) that allows users to dial phone numbers. The system is based on Canonical Correlation Analysis (CCA) and Steady-State Visual Evoked Potential (SSVEP). Through six buttons (9Hz, 10Hz, 11Hz, 12Hz, 13 Hz, 14Hz) displayed on the screen, subjects can choose the number by gazing at the computer interface. This proposed EEG (Electroencephalography) system has been implemented in Field-Programmable Gate Arrays (FPGA) and it features high accuracy, integration density, and low cost. These features are meaningful for implementing a real time SSVEP-based BCI.

KW - Accuracy

KW - Bandwidth

KW - Brain-computer interfaces

KW - Correlation

KW - Electroencephalography

KW - Field programmable gate arrays

KW - Visualization

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DO - 10.1109/ICCE-TW.2015.7216805

M3 - Conference contribution

AN - SCOPUS:84959487764

T3 - 2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015

SP - 110

EP - 111

BT - 2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2nd IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015

Y2 - 6 June 2015 through 8 June 2015

ER -

Feng CW, Chang JC, Chen WC, Fang WC. A reliable brain computer interface implemented on FPGA for mobile dialing system. 於 2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 110-111. 7216805. (2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015). doi: 10.1109/ICCE-TW.2015.7216805

A reliable brain computer interface implemented on FPGA for mobile dialing system

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