A Reference-Free Phase Noise Measurement Circuit Achieving 24.2-fs Periodic Jitter Sensitivity and 275-fs<inline-formula> <tex-math notation="LaTeX">$_{\mathrm{rms}}$</tex-math> </inline-formula> Resolution With Background Self-Calibration

This article presents an on-chip jitter/phase noise measurement (PNM) circuit that is reference-free and self-calibrated in situ in the background. <inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma $</tex-math> </inline-formula> time to digital converters (TDCs) are employed to measure cycle jitters of the signal under test and to digitize the power spectral density of phase noise. As a clean reference clock is not required for the PNM, the sensitivity of PNM is not limited by the reference source. The signal bandwidth of the TDC ranges from 100 kHz to 3.125 MHz, and the measured errors are less than 1 dB by a single-tone phase modulation (PM) test across the frequency range. Compared to the measurement results using a spectrum analyzer (Keysight N9030B), it demonstrates a jitter resolution of 275 fs<inline-formula> <tex-math notation="LaTeX">$_{\mathrm{rms}}$</tex-math> </inline-formula> with only 4.8% error, which is at least 3<inline-formula> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> finer compared to the prior art. This PNM is fabricated via a Taiwan Semiconductor Manufacturing Company (TSMC) 28-nm CMOS process, and the core area is 450 <inline-formula> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 453 <inline-formula> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula>m. The total power consumption is 15.83 mW.