A Reference-Free Phase Noise Measurement Circuit Achieving 24.2 fs Periodic Jitter Sensitivity and 275 fsrmsResolution with Background Self-Calibration

Wei Jhih Jian; Wei Zen Chen

doi:10.1109/VLSITechnologyandCir46769.2022.9830159

A Reference-Free Phase Noise Measurement Circuit Achieving 24.2 fs Periodic Jitter Sensitivity and 275 fs_rmsResolution with Background Self-Calibration

Wei Jhih Jian, Wei Zen Chen

電子研究所

研究成果: Conference contribution › 同行評審

摘要

This paper presents an on-chip jitter/phase noise measurement (PNM) circuit, which is reference-free and in-situ background self-calibrated. ?S Time to digital converters (?STDC) are employed to measure cycle jitters of the signal under test, and are capable of digitizing the power spectral density of phase noise. In accordance with the measurement results by using a spectrum analyzer, it demonstrates a jitter resolution of 275 fsrms with only 4.8% error, which is at least 3X finer compared to the prior art.

原文	English
主出版物標題	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	8-9
頁數	2
ISBN（電子）	9781665497725
DOIs	https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830159
出版狀態	Published - 2022
事件	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 - Honolulu, United States 持續時間: 12 6月 2022 → 17 6月 2022

出版系列

名字	Digest of Technical Papers - Symposium on VLSI Technology
卷	2022-June
ISSN（列印）	0743-1562

Conference

Conference	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
國家/地區	United States
城市	Honolulu
期間	12/06/22 → 17/06/22

存取文件

10.1109/VLSITechnologyandCir46769.2022.9830159

其它文件與鏈接

Link to publication in Scopus

引用此

Jian, W. J., & Chen, W. Z. (2022). A Reference-Free Phase Noise Measurement Circuit Achieving 24.2 fs Periodic Jitter Sensitivity and 275 fs_rmsResolution with Background Self-Calibration. 於 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 (頁 8-9). (Digest of Technical Papers - Symposium on VLSI Technology; 卷 2022-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830159

Jian, Wei Jhih ; Chen, Wei Zen. / A Reference-Free Phase Noise Measurement Circuit Achieving 24.2 fs Periodic Jitter Sensitivity and 275 fs_rmsResolution with Background Self-Calibration. 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Institute of Electrical and Electronics Engineers Inc., 2022. 頁 8-9 (Digest of Technical Papers - Symposium on VLSI Technology).

@inproceedings{8cc1818e6da24ae0927a967fdc853c58,

title = "A Reference-Free Phase Noise Measurement Circuit Achieving 24.2 fs Periodic Jitter Sensitivity and 275 fsrmsResolution with Background Self-Calibration",

abstract = "This paper presents an on-chip jitter/phase noise measurement (PNM) circuit, which is reference-free and in-situ background self-calibrated. ?S Time to digital converters (?STDC) are employed to measure cycle jitters of the signal under test, and are capable of digitizing the power spectral density of phase noise. In accordance with the measurement results by using a spectrum analyzer, it demonstrates a jitter resolution of 275 fsrms with only 4.8% error, which is at least 3X finer compared to the prior art.",

keywords = "?S time to digital converters, background self-calibration, phase noise measurement, reference-free and delay-line based frequency discriminator",

author = "Jian, {Wei Jhih} and Chen, {Wei Zen}",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 ; Conference date: 12-06-2022 Through 17-06-2022",

year = "2022",

doi = "10.1109/VLSITechnologyandCir46769.2022.9830159",

language = "English",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "8--9",

booktitle = "2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022",

address = "United States",

}

Jian, WJ & Chen, WZ 2022, A Reference-Free Phase Noise Measurement Circuit Achieving 24.2 fs Periodic Jitter Sensitivity and 275 fs_rmsResolution with Background Self-Calibration. 於 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Digest of Technical Papers - Symposium on VLSI Technology, 卷 2022-June, Institute of Electrical and Electronics Engineers Inc., 頁 8-9, 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022, Honolulu, United States, 12/06/22. https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830159

A Reference-Free Phase Noise Measurement Circuit Achieving 24.2 fs Periodic Jitter Sensitivity and 275 fs_rmsResolution with Background Self-Calibration. / Jian, Wei Jhih; Chen, Wei Zen.
2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Institute of Electrical and Electronics Engineers Inc., 2022. p. 8-9 (Digest of Technical Papers - Symposium on VLSI Technology; 卷 2022-June).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - A Reference-Free Phase Noise Measurement Circuit Achieving 24.2 fs Periodic Jitter Sensitivity and 275 fsrmsResolution with Background Self-Calibration

AU - Jian, Wei Jhih

AU - Chen, Wei Zen

PY - 2022

Y1 - 2022

N2 - This paper presents an on-chip jitter/phase noise measurement (PNM) circuit, which is reference-free and in-situ background self-calibrated. ?S Time to digital converters (?STDC) are employed to measure cycle jitters of the signal under test, and are capable of digitizing the power spectral density of phase noise. In accordance with the measurement results by using a spectrum analyzer, it demonstrates a jitter resolution of 275 fsrms with only 4.8% error, which is at least 3X finer compared to the prior art.

AB - This paper presents an on-chip jitter/phase noise measurement (PNM) circuit, which is reference-free and in-situ background self-calibrated. ?S Time to digital converters (?STDC) are employed to measure cycle jitters of the signal under test, and are capable of digitizing the power spectral density of phase noise. In accordance with the measurement results by using a spectrum analyzer, it demonstrates a jitter resolution of 275 fsrms with only 4.8% error, which is at least 3X finer compared to the prior art.

KW - ?S time to digital converters

KW - background self-calibration

KW - phase noise measurement

KW - reference-free and delay-line based frequency discriminator

UR - http://www.scopus.com/inward/record.url?scp=85135217312&partnerID=8YFLogxK

U2 - 10.1109/VLSITechnologyandCir46769.2022.9830159

DO - 10.1109/VLSITechnologyandCir46769.2022.9830159

M3 - Conference contribution

AN - SCOPUS:85135217312

T3 - Digest of Technical Papers - Symposium on VLSI Technology

SP - 8

EP - 9

BT - 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022

Y2 - 12 June 2022 through 17 June 2022

ER -

Jian WJ, Chen WZ. A Reference-Free Phase Noise Measurement Circuit Achieving 24.2 fs Periodic Jitter Sensitivity and 275 fs_rmsResolution with Background Self-Calibration. 於 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Institute of Electrical and Electronics Engineers Inc. 2022. p. 8-9. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.1109/VLSITechnologyandCir46769.2022.9830159