A reconfigurable video embedding transcoder based on H.264/AVC: Design tradeoffs and analysis

Chih Hung Li*, Wen-Hsiao Peng, Tihao Chiang

*此作品的通信作者

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

In this paper, we propose a system architecture for H.264/AVC video embedding transcoder (VET). In addition, the proposed platform-based design can seamlessly combine the MW-VET and decoder such that it can be dynamically configured to perform video decoding and transcoding alternatively or simultaneously. Furthermore, we perform the pruned design space exploration on the design of inter/intra prediction and the on-chip data bus width. Our proposed architecture provides a better tradeoff among execution cycles, hardware cost, resource utilization, and video quality because of the reconfigurable processing modules and the hybrid pipelining. As compared to the cascaded pixel domain transcoder that has the highest complexity, our hardware efficient VET can significantly reduce the hardware cost while maintaining similar rate-distortion performance. Finally, the proposed architecture is verified at system level using transaction level modeling (TLM) technique. From the simulation results, the proposed architecture with the best tradeoff configuration can achieve a transcoding rate up to 358 frames per second for SD video source while clocking at 162MHz.

原文English
主出版物標題2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
頁面852-855
頁數4
DOIs
出版狀態Published - 19 九月 2008
事件2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 - Seattle, WA, United States
持續時間: 18 五月 200821 五月 2008

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
ISSN(列印)0271-4310

Conference

Conference2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
國家/地區United States
城市Seattle, WA
期間18/05/0821/05/08

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