TY - GEN
T1 - A reconfigurable MAC architecture implemented with mixed-Vt standard cell library
AU - Wang, Li Rong
AU - Chiu, Yi Wei
AU - Hu, Chia Lin
AU - Tu, Ming Hsien
AU - Jou, Shyh-Jye
AU - Lee, Chung Len
PY - 2008
Y1 - 2008
N2 - In this paper, a 32-bit reconfigurable multiplication-accumulation architecture, which can execute flexibly one 32x32, two 16x16 or four 8x8 two's complement multiply-accumulation, is proposed and demonstrated. It is based on the modified Booth encoding scheme and designed with techniques of reducing sign-extension bits, removing one extra partial product row and adjusting the positions of hot signals but with elegant modifications. It is implemented with a 130nm mixed-Vt CMOS standard cell library and shows saving of area and power consumption by approximately 16% and 14% respectively as compared to the previous design.
AB - In this paper, a 32-bit reconfigurable multiplication-accumulation architecture, which can execute flexibly one 32x32, two 16x16 or four 8x8 two's complement multiply-accumulation, is proposed and demonstrated. It is based on the modified Booth encoding scheme and designed with techniques of reducing sign-extension bits, removing one extra partial product row and adjusting the positions of hot signals but with elegant modifications. It is implemented with a 130nm mixed-Vt CMOS standard cell library and shows saving of area and power consumption by approximately 16% and 14% respectively as compared to the previous design.
UR - http://www.scopus.com/inward/record.url?scp=51749093050&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2008.4542195
DO - 10.1109/ISCAS.2008.4542195
M3 - Conference contribution
AN - SCOPUS:51749093050
SN - 9781424416844
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 3426
EP - 3429
BT - 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
T2 - 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
Y2 - 18 May 2008 through 21 May 2008
ER -