A Reconfigurable In-SRAM Computing Architecture for DCNN Applications

Yu Hsien Lin; Chi Liu; Chia Lin Hu; Kang Yu Chang; Jia Yin Chen; Shyh Jye Jou

doi:10.1109/VLSI-DAT52063.2021.9427349

A Reconfigurable In-SRAM Computing Architecture for DCNN Applications

Yu Hsien Lin, Chi Liu, Chia Lin Hu, Kang Yu Chang, Jia Yin Chen, Shyh Jye Jou

電子研究所

研究成果: Conference contribution › 同行評審

5 引文斯高帕斯（Scopus）

摘要

A methodology for Artificial Intelligence (AI) edge Deep Learning Neural Network (DNN) hardware design to increase the flexibility of each layer is emergent required. In order to support different DNN layers, a reconfigurable Universal Computation Element (UCE-R) is proposed. The UCE-R has its own controller and several UCE-Rs can be integrated to form a Reconfigurable UDNN (UDNN-R) engine for use in different kinds of AI edge applications. The design of UCE-R is implemented by using TSMC CMOS 28 um process. An UDNN-R is integrated for a Mobile-Net application.

原文	English
主出版物標題	2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings
發行者	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子）	9781665419154
DOIs	https://doi.org/10.1109/VLSI-DAT52063.2021.9427349
出版狀態	Published - 19 4月 2021
事件	2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Hsinchu, 台灣持續時間: 19 4月 2021 → 22 4月 2021

出版系列

名字	2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings

Conference

Conference	2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021
國家/地區	台灣
城市	Hsinchu
期間	19/04/21 → 22/04/21

存取文件

10.1109/VLSI-DAT52063.2021.9427349

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Link to publication in Scopus

引用此

Lin, Y. H., Liu, C., Hu, C. L., Chang, K. Y., Chen, J. Y., & Jou, S. J. (2021). A Reconfigurable In-SRAM Computing Architecture for DCNN Applications. 於 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings 文章 9427349 (2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT52063.2021.9427349

Lin, Yu Hsien ; Liu, Chi ; Hu, Chia Lin 等. / A Reconfigurable In-SRAM Computing Architecture for DCNN Applications. 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2021. (2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings).

@inproceedings{52350e89f05548428d58bf4856c814a3,

title = "A Reconfigurable In-SRAM Computing Architecture for DCNN Applications",

abstract = "A methodology for Artificial Intelligence (AI) edge Deep Learning Neural Network (DNN) hardware design to increase the flexibility of each layer is emergent required. In order to support different DNN layers, a reconfigurable Universal Computation Element (UCE-R) is proposed. The UCE-R has its own controller and several UCE-Rs can be integrated to form a Reconfigurable UDNN (UDNN-R) engine for use in different kinds of AI edge applications. The design of UCE-R is implemented by using TSMC CMOS 28 um process. An UDNN-R is integrated for a Mobile-Net application. ",

author = "Lin, {Yu Hsien} and Chi Liu and Hu, {Chia Lin} and Chang, {Kang Yu} and Chen, {Jia Yin} and Jou, {Shyh Jye}",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 ; Conference date: 19-04-2021 Through 22-04-2021",

year = "2021",

month = apr,

day = "19",

doi = "10.1109/VLSI-DAT52063.2021.9427349",

language = "English",

series = "2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings",

address = "美國",

}

Lin, YH, Liu, C, Hu, CL, Chang, KY, Chen, JY & Jou, SJ 2021, A Reconfigurable In-SRAM Computing Architecture for DCNN Applications. 於 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings., 9427349, 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings, Institute of Electrical and Electronics Engineers Inc., 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021, Hsinchu, 台灣, 19/04/21. https://doi.org/10.1109/VLSI-DAT52063.2021.9427349

A Reconfigurable In-SRAM Computing Architecture for DCNN Applications. / Lin, Yu Hsien; Liu, Chi; Hu, Chia Lin 等.
2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2021. 9427349 (2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings).

研究成果: Conference contribution › 同行評審

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T1 - A Reconfigurable In-SRAM Computing Architecture for DCNN Applications

AU - Lin, Yu Hsien

AU - Liu, Chi

AU - Hu, Chia Lin

AU - Chang, Kang Yu

AU - Chen, Jia Yin

AU - Jou, Shyh Jye

PY - 2021/4/19

Y1 - 2021/4/19

N2 - A methodology for Artificial Intelligence (AI) edge Deep Learning Neural Network (DNN) hardware design to increase the flexibility of each layer is emergent required. In order to support different DNN layers, a reconfigurable Universal Computation Element (UCE-R) is proposed. The UCE-R has its own controller and several UCE-Rs can be integrated to form a Reconfigurable UDNN (UDNN-R) engine for use in different kinds of AI edge applications. The design of UCE-R is implemented by using TSMC CMOS 28 um process. An UDNN-R is integrated for a Mobile-Net application.

AB - A methodology for Artificial Intelligence (AI) edge Deep Learning Neural Network (DNN) hardware design to increase the flexibility of each layer is emergent required. In order to support different DNN layers, a reconfigurable Universal Computation Element (UCE-R) is proposed. The UCE-R has its own controller and several UCE-Rs can be integrated to form a Reconfigurable UDNN (UDNN-R) engine for use in different kinds of AI edge applications. The design of UCE-R is implemented by using TSMC CMOS 28 um process. An UDNN-R is integrated for a Mobile-Net application.

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U2 - 10.1109/VLSI-DAT52063.2021.9427349

DO - 10.1109/VLSI-DAT52063.2021.9427349

M3 - Conference contribution

AN - SCOPUS:85106658121

T3 - 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings

BT - 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021

Y2 - 19 April 2021 through 22 April 2021

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Lin YH, Liu C, Hu CL, Chang KY, Chen JY, Jou SJ. A Reconfigurable In-SRAM Computing Architecture for DCNN Applications. 於 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2021. 9427349. (2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings). doi: 10.1109/VLSI-DAT52063.2021.9427349

A Reconfigurable In-SRAM Computing Architecture for DCNN Applications

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