A Reconfigurable Deep Neural Network on Chip Design with Flexible Convolutional Operations

Kun Chih Chen, Yi Sheng Liao

研究成果: Conference contribution同行評審

3 引文 斯高帕斯(Scopus)

摘要

The designs of deep neural network (DNN) accelerators have gradually gained attention due to the increased demand for real-Time AI applications. On the other hand, due to the diverse applications, kernel sizes and shapes for the involved convolutional operation in the target DNN model are not fixed. Therefore, it is necessary to design a reconfigurable DNN accelerator to cover different kernel sizes for convolutional operation in DNNs. However, due to the worst-case design policy, the designers usually select the largest kernel size as the design parameter to implement the DNN accelerator, which leads to lower hardware utilization. The reason is that the conventional array-based DNN design method restricts the efficiency of data delivery. Besides, the complicated data flow between neuron layers of DNN models counteracts the benefit of the involved data reuse method. To mitigate the design problems of complicated data flow on DNN accelerators, Network-on-Chip (NoC) interconnection has become an emerging technology to realize the Deep Neural Network on Chip (DNNoC). Compared with the conventional array-based DNN acceleration design, the DNNoC design supports flexible data flow, which leverages reconfigurable DNN accelerator implementations. In this work, we leverage the flexible NoC interconnection and propose a hybrid input/weight reuse method to reduce memory access. In addition, our proposed hybrid input/weight reuse method supports arbitrary kernel sizes for flexible convolutional operations. Compared with the related works, the proposed reconfigurable DNNoC with flexible convolutional operations helps to improve the utilization of computational capability in a PE by 1 % to 34 %, reduce memory access by 66% to 85%, which helps to improve 40% to 117% throughput.

原文English
主出版物標題2022 15th International Workshop on Network on Chip Architectures, NoCArc 2022 - In conjunction with the 55th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2022
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781665455893
DOIs
出版狀態Published - 2022
事件15th IEEE/ACM International Workshop on Network on Chip Architectures, NoCArc 2022 - Chicago, 美國
持續時間: 2 10月 2022 → …

出版系列

名字2022 15th International Workshop on Network on Chip Architectures, NoCArc 2022 - In conjunction with the 55th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2022

Conference

Conference15th IEEE/ACM International Workshop on Network on Chip Architectures, NoCArc 2022
國家/地區美國
城市Chicago
期間2/10/22 → …

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