@inproceedings{bbfe0ab317a64e559452542acb46ff9c,
title = "A Real Time Super Resolution Accelerator with Tilted Layer Fusion",
abstract = "Deep learning based superresolution achieves high-quality results, but its heavy computational workload, large buffer, and high external memory bandwidth inhibit its usage in mobile devices. To solve the above issues, this paper proposes a real-time hardware accelerator with the tilted layer fusion method that reduces the external DRAM bandwidth by 92% and just needs 102KB on-chip memory. The design implemented with a 40nm CMOS process achieves 1920xl080@60fps throughput with 544. 3K gate count when running at 600MHz; it has higher throughput and lower area cost than previous designs.",
keywords = "Convolutional Neural Networks (CNNs), deep learning accelerators, layer fusion, real-time, super-resolution",
author = "Huang, {An Jung} and Hsu, {Kai Chieh} and Chang, {Tian Sheuan}",
note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022 ; Conference date: 27-05-2022 Through 01-06-2022",
year = "2022",
doi = "10.1109/ISCAS48785.2022.9937448",
language = "English",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "2665--2669",
booktitle = "IEEE International Symposium on Circuits and Systems, ISCAS 2022",
address = "美國",
}