A Progressive Performance Boosting Strategy for 3-D Charge-Trap NAND Flash

The growing demands of large-capacity flash-based storages have facilitated the downscaling process of NAND flash memory. However, the downscaling of traditional planar floating-gate flash memory faces several challenges. Therefore, new NAND flash technologies have been explored to provide larger capacity with low cost. Among these new technologies, the 3-D charge-trap flash is regarded as one of the most promising candidates. The 3-D charge-trap flash is composed of several gate-stack layers and vertical cylindrical channels to provide high-density and low cell-to-cell interference. Owing to the cylindrical geometry of vertical channels, the access performance of each page in one block is distinctive, and this situation is exacerbated in the 3-D charge-trap flash with the fast-growing number of gate-stack layers. In this paper, a progressive performance boosting strategy is proposed to boost the performance of 3-D charge-trap flash by utilizing its asymmetric page access speed feature. A series of experiments was conducted to demonstrate the capability of the proposed strategy on improving the access performance of 3-D charge-trap flash.