A platform based bus-interleaved architecture for de-blocking filter in H.264/MPEG-4 AVC

Shih Chien Chang*, Wen-Hsiao Peng, Shih Hao Wang, Tihao Chiang

*此作品的通信作者

研究成果: Article同行評審

38 引文 斯高帕斯(Scopus)

摘要

In this paper, we proposed a platform based bus-interleaved architecture for the de-blocking filter in H.264. Specifically, to efficiently use the bus bandwidth, we classify the filtering mode into 8 types and use an adaptive transmission scheme to avoid redundant data transfer. Moreover, to reduce the processing latency, we use a bus-interleaved architecture for conducting data transmission and filtering in parallel. As compared to the state-of-the-art designs, our scheme offers 1.6× to 7× performance improvement. While clocking at 100MHz, our design can support 2560×12800Hz processing throughput. The proposed design is suitable for low cost and real-time applications. Moreover, it can be easily applied in system-on-chip design.

原文English
頁(從 - 到)249-255
頁數7
期刊IEEE Transactions on Consumer Electronics
51
發行號1
DOIs
出版狀態Published - 1 二月 2005

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