A pipelined multiplier-accumulator using a high-speed, low-power static and dynamic full adder design

Shyh-Jye Jou*, Chang Yu Chen, En Chung Yang, Chau-Chin Su

*此作品的通信作者

研究成果: Article同行評審

27 引文 斯高帕斯(Scopus)

摘要

This paper proposes a new pipelined full-adder circuit structure for the implementation of pipelined arithmetic modules. With both static and dynamic structures, it has the advantages of high operational speed, smallest transistor count, and the low power/speed ratio. The adder cell is then used to design a pipelined 8 × 8-b multiplier-accumulator (MAC). In this MAC, a special pipelined structure is designed to reduce the latency. The MAC is fabricated in a 0.8-μm single-poly-double-metal CMOS process. The post-layout simulation shows that the pipelined 1-b full adder can work up to 350 MHz with a 3 V power supply. The whole MAC chip that contains 4200 transistors is measured to operate a 125 MIz using 3.3 V power supply.

原文English
頁(從 - 到)114-118
頁數5
期刊IEEE Journal of Solid-State Circuits
32
發行號1
DOIs
出版狀態Published - 1 1月 1997

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