A parameterized low power design for the variable-length discrete Fourier transform using dynamic pipelining

Jiun-In  Guo*, Chih Da Chien, Chien Chang Lin

*此作品的通信作者

研究成果: Conference article同行評審

摘要

This paper presents a parameterized low power design for the one-dimensional discrete Fourier transform (DFT) of variable lengths. By combining the cyclic convolution formulation, block-based distributed arithmetic, dynamic pipeline technique, and Cooley-Tukey decomposition together, we have developed a parameterized hardware design for the DFT of variable lengths ranging from 256 to 4096 points and with different modes of performance, which facilitates the performance-driven design considerations in terms of power consumption and processing speeds. This feature is beneficial to developing a parameterized DFT Intellectual Property (IP) core for meeting the system requirements of different silicon-on-a-chip applications as compared with the existing fixed length DFT designs.

原文English
頁(從 - 到)V293-V296
期刊Proceedings - IEEE International Symposium on Circuits and Systems
5
DOIs
出版狀態Published - 2003
事件Proceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand
持續時間: 25 5月 200328 5月 2003

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