A Novel Technology Mapper for Complex Universal Gates

Meng Che Wu, Ai Quoc Dao, Po-Hung Lin

研究成果: Conference contribution同行評審

摘要

Complex universal logic gates, which may have higher density and flexibility than basic logic gates and look-up tables (LUT), are useful for cost-effective or security-oriented VLSI design requirements. However, most of the technology mapping algorithms aim to optimize combinational logic with basic standard cells or LUT components. It is desirable to investigate optimal technology mappers for complex universal gates in addition to basic standard cells and LUT components. This paper proposes a novel technology mapper for complex universal gates with a tight integration of the following techniques: Boolean network simulation with permutation classification, supergate library construction, dynamic programming based cut enumeration, Boolean matching with optimal universal cell covering. Experimental results show that the proposed method outperforms the state-of-the-art technology mapper in ABC, in terms of both area and delay.

原文English
主出版物標題Proceedings of the 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021
發行者Institute of Electrical and Electronics Engineers Inc.
頁面475-480
頁數6
ISBN(電子)9781450379991
DOIs
出版狀態Published - 18 1月 2021
事件26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021 - Virtual, Online, Japan
持續時間: 18 1月 202121 1月 2021

出版系列

名字Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021
國家/地區Japan
城市Virtual, Online
期間18/01/2121/01/21

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