A novel structure for digital image stabilizer

Guan Rong Chen; Yeou Min Yeh; Sheng-Jyh Wang; Huang Cheng Chiang

doi:10.1109/APCCAS.2000.913416

A novel structure for digital image stabilizer

Guan Rong Chen^*, Yeou Min Yeh, Sheng-Jyh Wang, Huang Cheng Chiang

^*此作品的通信作者

研究成果 › 同行評審

12 引文斯高帕斯（Scopus）

摘要

In this paper, a new architecture for digital image stabilizer (DIS) is presented. The system utilizes a matching algorithm on the Gray-coded bit-plane of the video sequence, which greatly reduces the complexity and enables the real-time processing capability in its motion estimating mechanism. According to the algorithm, a flexible system architecture containing software and hardware blocks is proposed. The proposed design is computationally efficient and is thus well suited as a low-cost solution for DIS in camcoders. In practice, the system has been validated on a mixed FPGA/DSP-based prototype.

原文	English
頁面	101-104
頁數	4
DOIs	https://doi.org/10.1109/APCCAS.2000.913416
出版狀態	Published - 2000
事件	2000 IEEE Asia-Pacific Conference on Circuits and Systems: Electronic Communication Systems - Tianjin, 中國持續時間: 4 12月 2000 → 6 12月 2000

Conference

Conference	2000 IEEE Asia-Pacific Conference on Circuits and Systems: Electronic Communication Systems
國家/地區	中國
城市	Tianjin
期間	4/12/00 → 6/12/00

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10.1109/APCCAS.2000.913416

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引用此

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title = "A novel structure for digital image stabilizer",

abstract = "In this paper, a new architecture for digital image stabilizer (DIS) is presented. The system utilizes a matching algorithm on the Gray-coded bit-plane of the video sequence, which greatly reduces the complexity and enables the real-time processing capability in its motion estimating mechanism. According to the algorithm, a flexible system architecture containing software and hardware blocks is proposed. The proposed design is computationally efficient and is thus well suited as a low-cost solution for DIS in camcoders. In practice, the system has been validated on a mixed FPGA/DSP-based prototype.",

author = "Chen, {Guan Rong} and Yeh, {Yeou Min} and Sheng-Jyh Wang and Chiang, {Huang Cheng}",

year = "2000",

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AU - Chen, Guan Rong

AU - Yeh, Yeou Min

AU - Wang, Sheng-Jyh

AU - Chiang, Huang Cheng

PY - 2000

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N2 - In this paper, a new architecture for digital image stabilizer (DIS) is presented. The system utilizes a matching algorithm on the Gray-coded bit-plane of the video sequence, which greatly reduces the complexity and enables the real-time processing capability in its motion estimating mechanism. According to the algorithm, a flexible system architecture containing software and hardware blocks is proposed. The proposed design is computationally efficient and is thus well suited as a low-cost solution for DIS in camcoders. In practice, the system has been validated on a mixed FPGA/DSP-based prototype.

AB - In this paper, a new architecture for digital image stabilizer (DIS) is presented. The system utilizes a matching algorithm on the Gray-coded bit-plane of the video sequence, which greatly reduces the complexity and enables the real-time processing capability in its motion estimating mechanism. According to the algorithm, a flexible system architecture containing software and hardware blocks is proposed. The proposed design is computationally efficient and is thus well suited as a low-cost solution for DIS in camcoders. In practice, the system has been validated on a mixed FPGA/DSP-based prototype.

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DO - 10.1109/APCCAS.2000.913416

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T2 - 2000 IEEE Asia-Pacific Conference on Circuits and Systems: Electronic Communication Systems

Y2 - 4 December 2000 through 6 December 2000

ER -

A novel structure for digital image stabilizer

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