A novel self-aligned shallow trench isolation cell for 90nm 4Gbit NAND flash EEPROM s

Masayuki Ichige*, Yuji Takeuchi, Kikuko Sugimae, Atsuhiro Sato, Michiharu Matsui, Takeshi Kamigaichi, Hiroyuki Kutsukake, Yutaka Ishibashi, Masanobu Saito, Seiichi Mori, Hisataka Meguro, Shoichi Miyazaki, Tadashi Miwa, Shinya Takahashi, Tadashi Iguchi, Naoto Kawai, Susumu Tamon, Norihisa Arai, Hideyuki Kamata, Toshifumi MinamiHirohisa Iizuka, Masaaki Higashitani, Tuan Pham, Gertjan Hemink, Masaki Momodomi, Shirota Riichiro

*此作品的通信作者

研究成果: Conference article同行評審

10 引文 斯高帕斯(Scopus)

摘要

A new self-aligned shallow trench isolation cell for 90 nm 4 Gbit NAND flash EEPROMs was discussed. Shallow trench isolation (STI) which is used to reduce memory cell size was also studied. It was found that this technology can be applied to 2 Gbit binary and 4 Gbit multi level memory cells.

原文English
頁(從 - 到)89-90
頁數2
期刊Digest of Technical Papers - Symposium on VLSI Technology
DOIs
出版狀態Published - 2003
事件2003 Symposium on VLSI Technology - Kyoto, Japan
持續時間: 10 6月 200312 6月 2003

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