A novel programmable digital signal processor for multimedia applications

Li Chun Lin*, Tay Jyi Lin, Chen Chia Lee, Chie Min Chao, Shin Kai Chen, Chia Hsien Liu, Pi Chen Hsiao, Chih-Wei Liu, Chein Wei Jen

*此作品的通信作者

    研究成果: Paper同行評審

    1 引文 斯高帕斯(Scopus)

    摘要

    This paper presents a novel DSP architecture for multimedia applications. The DSP core is a simple RISC processor from the programmer's view, which has a high-performance DSP unit and the applications can be easily targeted on the RISC shell to reduce the development time. Moreover, the DSP unit is itself a fully-programmable 4-way VLIW datapath, which has a novel ping-pong register file. To smooth the instruction execution of the two-level programmable DSP processor and improve the code density, we propose a hierarchical encoding scheme for variable-length instructions. The simulations show that our DSP has comparable performance with state-of-the-art DSP architectures, and the hierarchical instruction encoding saves 31%-64% code sizes compared to the fixed-length instruction encoding.

    原文English
    頁面121-124
    頁數4
    DOIs
    出版狀態Published - 12月 2004
    事件2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan
    持續時間: 6 12月 20049 12月 2004

    Conference

    Conference2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
    國家/地區Taiwan
    城市Tainan
    期間6/12/049/12/04

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