A Novel Method of Electrical Measurement for Stacking Error in 3D/2.5D Integration

Shih Wei Lee; Shu Chiao Kuo; Kuan-Neng Chen

doi:10.1166/jnn.2018.14204

A Novel Method of Electrical Measurement for Stacking Error in 3D/2.5D Integration

Shih Wei Lee, Shu Chiao Kuo, Kuan-Neng Chen

研究成果: Article › 同行評審

摘要

A novel method for the inspection of the stacking misalignment in three-dimensional integration circuit (3DIC) by using electrical measurement is proposed. The metal line pattern designed in this paper combined with bump-less TSV fabrication process can successfully detect the direction and quantity of stacking fault. In addition, circuit combined with testing structure can be developed and simulated by using the current mirror concept and offered measurements with better efficiency.

原文	American English
頁（從 - 到）	1066-1069
頁數	4
期刊	Journal of Nanoscience and Nanotechnology
卷	18
發行號	2
DOIs	https://doi.org/10.1166/jnn.2018.14204
出版狀態	Published - 2月 2018

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10.1166/jnn.2018.14204

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title = "A Novel Method of Electrical Measurement for Stacking Error in 3D/2.5D Integration",

abstract = "A novel method for the inspection of the stacking misalignment in three-dimensional integration circuit (3DIC) by using electrical measurement is proposed. The metal line pattern designed in this paper combined with bump-less TSV fabrication process can successfully detect the direction and quantity of stacking fault. In addition, circuit combined with testing structure can be developed and simulated by using the current mirror concept and offered measurements with better efficiency.",

keywords = "Electrical Measurement, Misalignment, TSV 3D-IC, Three-dimensional (3D) integration",

author = "Lee, {Shih Wei} and Kuo, {Shu Chiao} and Kuan-Neng Chen",

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N2 - A novel method for the inspection of the stacking misalignment in three-dimensional integration circuit (3DIC) by using electrical measurement is proposed. The metal line pattern designed in this paper combined with bump-less TSV fabrication process can successfully detect the direction and quantity of stacking fault. In addition, circuit combined with testing structure can be developed and simulated by using the current mirror concept and offered measurements with better efficiency.

AB - A novel method for the inspection of the stacking misalignment in three-dimensional integration circuit (3DIC) by using electrical measurement is proposed. The metal line pattern designed in this paper combined with bump-less TSV fabrication process can successfully detect the direction and quantity of stacking fault. In addition, circuit combined with testing structure can be developed and simulated by using the current mirror concept and offered measurements with better efficiency.

KW - Electrical Measurement

KW - Misalignment

KW - TSV 3D-IC

KW - Three-dimensional (3D) integration

U2 - 10.1166/jnn.2018.14204

DO - 10.1166/jnn.2018.14204

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A Novel Method of Electrical Measurement for Stacking Error in 3D/2.5D Integration

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