A novel low-cost high-performance VLSI architecture for MPEG-4 AVC/H.264 CAVLC decoding

The demand of high quality video and high data compression enables the MPEG-4 AVC/H.264 adopting the Context-based Adaptive Variable Length Code (CAVLC) technique as contrary to the traditional MPEG-4 VLC techniques. This paper presents a novel low-cost, high-performance VLSI architecture design for MPEG-4 AVC/H.264 CAVLC decoding. In the proposed design, we exploit five different techniques to reduce both the hardware cost and power consumption, as well as increase the data throughput rate. They are PCCF (Partial combinational component Freezing), HLLT (Hierarchical logic for Look-up tables), ZTEBA (Zero-left table elimination by arithmetic), IDS (Interleaved Double Stacks), and ZCS (Zero Codeword Skip). As a result, the proposed design can decode every syntax element per cycle. The synthesis result shows that the design achieves the maximum speed at 175 MHz. When we synthesize the proposed design at clock constraint of 125MHz, the hardware cost is about 4720 gates under a 0.18um CMOS technology, which achieves the real-time processing requirement for H.264 video decoding on HD1080i format video.