@inproceedings{3ec17db0d0944c31916c95cccad91dda,
title = "A novel glitch reduction circuitry for binary-weighted DAC",
abstract = "This paper presents a high-speed, low-glitch, and low-power design for a 10-bit binary-weighted current-steering digital-to-analog converter (DAC). Instead of using large input buffers, the proposed design uses variable-delay buffers to compensate for the delay difference among different bits, and to reduce high glitch energy from 132pVs to 1.36pVs during major code transition. The spurious free dynamic range (SFDR) has been improved over 10dB compared to the conventional DAC without variable-delay buffers. This chip was implemented in a standard 0.18um CMOS technology, occupies 1.1mm2 core area, and dissipates 19mW from a single 1.8V power supply.",
keywords = "Binary-weighted, DAC, variable-delay buffer",
author = "Chou, {Fang Ting} and Chen, {Chia Min} and Chen, {Zong Yi} and Chung-Chih Hung",
year = "2015",
month = feb,
day = "5",
doi = "10.1109/APCCAS.2014.7032764",
language = "English",
series = "IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "February",
pages = "240--243",
booktitle = "2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014",
address = "美國",
edition = "February",
note = "2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014 ; Conference date: 17-11-2014 Through 20-11-2014",
}