A novel glitch reduction circuitry for binary-weighted DAC

Fang Ting Chou, Chia Min Chen, Zong Yi Chen, Chung-Chih Hung

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

This paper presents a high-speed, low-glitch, and low-power design for a 10-bit binary-weighted current-steering digital-to-analog converter (DAC). Instead of using large input buffers, the proposed design uses variable-delay buffers to compensate for the delay difference among different bits, and to reduce high glitch energy from 132pVs to 1.36pVs during major code transition. The spurious free dynamic range (SFDR) has been improved over 10dB compared to the conventional DAC without variable-delay buffers. This chip was implemented in a standard 0.18um CMOS technology, occupies 1.1mm2 core area, and dissipates 19mW from a single 1.8V power supply.

原文English
主出版物標題2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014
發行者Institute of Electrical and Electronics Engineers Inc.
頁面240-243
頁數4
版本February
ISBN(電子)9781479952304
DOIs
出版狀態Published - 5 2月 2015
事件2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014 - Ishigaki Island, Okinawa, Japan
持續時間: 17 11月 201420 11月 2014

出版系列

名字IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
號碼February
2015-February

Conference

Conference2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014
國家/地區Japan
城市Ishigaki Island, Okinawa
期間17/11/1420/11/14

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