A novel design of high-speed divide-by-3/4 counter for a dual-modulus prescaler

Yi Shing Shih*, Jenn-Hawn Tarng

*此作品的通信作者

研究成果: Article同行評審

2 引文 斯高帕斯(Scopus)

摘要

A novel design for a high-speed divide-by-3/4 counter is presented. The proposed design reduces not only the critical path delay but also the feedback path delay, hence it can increase the operating speed. With this divide-by-3/4 counter, a divide-by-127/128 dual-modulus prescaler (DMP), implemented in 0.18μm CMOS technology, shows a maximum operating frequency of 7.0 GHz with 2.4mW power consumption at 1.8V supply voltage, which has 25% speed improvement and still consumes less power as well compared to the recently-reported one.

原文English
頁(從 - 到)276-280
頁數5
期刊IEICE Electronics Express
3
發行號12
DOIs
出版狀態Published - 25 6月 2006

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