A novel array-based test methodology for local process variation monitoring

Tseng Chin Luo*, Chia-Tso Chao, Michael Shien Yang Wu, Kuo Tsai Li, Chin C. Hsia, Huan Chi Tseng, Philip A. Fisher, Chuen Uan Huang, Yuan Yao Chang, Samuel C. Pan, Konrad K.L. Young

*此作品的通信作者

    研究成果: Article同行評審

    11 引文 斯高帕斯(Scopus)

    摘要

    As process technologies continually advance, local process variation has greatly increased and gradually become one of the most critical factors for integrated circuit manufacturing. To monitor local process variation, a large number of devices-under-test (DUTs) in close proximity must be measured. In this paper, we present a novel array-based test structure to characterize local process variation with limited area overhead. The proposed test structure can guarantee high measurement accuracy by application of the test techniques proposed in this paper: hardware IR compensation, voltage bias elevation, and leakage-current cancelation. Furthermore, the DUT layout need not be modified for the proposed test structure. Thus, the measured variation exactly reflects the reality in the manufacturing environment. The measured results from the few most advanced process-technology nodes demonstrate the effectiveness and efficiency of the proposed test structure in quantifying local process variation.

    原文English
    文章編號5648466
    頁(從 - 到)280-293
    頁數14
    期刊IEEE Transactions on Semiconductor Manufacturing
    24
    發行號2
    DOIs
    出版狀態Published - 5月 2011

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