A novel analog physical synthesis methodology integrating existent design expertise

Po Hsun Wu, Po-Hung Lin, Tung Chieh Chen, Ching Feng Yeh, Xin Li, Tsung Yi Ho

研究成果: Article同行評審

24 引文 斯高帕斯(Scopus)

摘要

Analog layout design has been a manual, time-consuming, and error-prone task for decades. To speed up layout design time for a new design, analog layout designers prefer referring to legacy designs and layouts rather than starting from scratch, or thoroughly applying placement and routing tools because legacy layouts contain pretty much design expertise. Motivated by such layout design process, this paper presents the first knowledge-based physical synthesis methodology to generate new layouts by integrating existent design expertise. The proposed approach can automatically analyze legacy design data including circuits, layouts, and constraints, extract matched sub-circuits between new and legacy designs, and generate multiple layouts for the new design by utilizing the quality-approved legacy layouts as much as possible. Experimental results show that the proposed methodology can achieve high layout reusage rate, and hence the designers' layout preference can be successfully reserved.

原文English
文章編號6981934
頁(從 - 到)199-212
頁數14
期刊IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
34
發行號2
DOIs
出版狀態Published - 1 二月 2015

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