A New Vertical Double Diffused MOSFET—The Self-Aligned Terraced-Gate MOSFET

Daisuke Ueda, Hiromitsu Takagi, Gota Kano

研究成果: Article同行評審

18 引文 斯高帕斯(Scopus)

摘要

A new power MOSFET structure with a Self-aligned Terraced Gate (STGMOSFET) is demonstrated. The unique gate structure of the STGMOSFET reduces the parasitic gate capacitances, resulting in improved high-frequency performance. The STGMOSFET structure was used to design a 3.5 mm X 3.5 mm transistor. This chip had an on-resistance of 2.3 n and a 500-V source- drain breakdown voltage. It exhibited excellent high-frequency performance with a cut-off frequency of 100 MHz, and rise and fall times of 5 and 20 nS, respectively.

原文English
頁(從 - 到)416-420
頁數5
期刊IEEE Transactions on Electron Devices
31
發行號4
DOIs
出版狀態Published - 1 1月 1984

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