A new three-dimensional capacitor model for accurate simulation of parasitic capacitances in nanoscale MOSFETs

Jyh-Chyurn Guo*, Chih Ting Yeh

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    研究成果: Article同行評審

    12 引文 斯高帕斯(Scopus)

    摘要

    A new 3-D gate capacitor model is developed to accurately calculate the parasitic capacitances of nanoscale CMOS devices. The dependences on gate length and width, gate electrode and dielectric thicknesses, gate-to-contact spacing, and contact dimension and geometry are fully incorporated in this model. The accuracy is certified by an excellent match with the 3-D interconnection simulation results for three structures with strip, square, and circular contacts. The features of being free from fitting parameters and proven accuracy over various geometries make this model useful for nanoscale MOSFET parasitic capacitance simulation and analysis. Furthermore, the developed capacitor model in the form of multidimensional integral can easily be deployed in general circuit simulators. This model predicts that the parasitic capacitance Cof dominates around 25% of the intrinsic gate capacitance (Cgint) in 80-nm MOSFETs and that the near nonscalability with gate length brings the weighting factor C of/Cgint above 30%/40%/60% in 65-/45-/32-nm devices. It actually exceeds the limitation defined by the most updated ITRS and reveals itself as a show-stopper in high-speed and high-frequency circuit design.

    原文English
    頁(從 - 到)1598-1607
    頁數10
    期刊IEEE Transactions on Electron Devices
    56
    發行號8
    DOIs
    出版狀態Published - 26 6月 2009

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