A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI

Chung-Yu Wu; Ming-Dou Ker; Chung Yuan Lee; Joe Ko; Larry Lin

doi:10.1109/CICC.1991.164085

A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI

Chung-Yu Wu^*, Ming-Dou Ker, Chung Yuan Lee, Joe Ko, Larry Lin

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電子研究所

研究成果: Conference contribution › 同行評審

3 引文斯高帕斯（Scopus）

摘要

A novel CMOS on-chip ESD (electrostatic discharge) protection circuit which consists of dual parasitic SCR structures is proposed. Experimental results show that it can successfully provide for negative and positive ESD protection with failure thresholds greater than ±1 kV and ±10 kV in machine-mode (MM) and human-body-mode (HBM) testing, respectively. Moreover, low triggering voltages in both SCRs can be readily achieved without involving device or junction breakdown.

原文	English
主出版物標題	Proceedings of the Custom Integrated Circuits Conference
發行者	Publ by IEEE
ISBN（列印）	0780300157
DOIs	https://doi.org/10.1109/CICC.1991.164085
出版狀態	Published - 1 12月 1991
事件	Proceedings of the IEEE 1991 Custom Integrated Circuits Conference - San Diego, CA, USA 持續時間: 12 5月 1991 → 15 5月 1991

出版系列

名字	Proceedings of the Custom Integrated Circuits Conference
ISSN（列印）	0886-5930

Conference

Conference	Proceedings of the IEEE 1991 Custom Integrated Circuits Conference
城市	San Diego, CA, USA
期間	12/05/91 → 15/05/91

存取文件

10.1109/CICC.1991.164085

其它文件與鏈接

Link to publication in Scopus

引用此

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title = "A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI",

abstract = "A novel CMOS on-chip ESD (electrostatic discharge) protection circuit which consists of dual parasitic SCR structures is proposed. Experimental results show that it can successfully provide for negative and positive ESD protection with failure thresholds greater than ±1 kV and ±10 kV in machine-mode (MM) and human-body-mode (HBM) testing, respectively. Moreover, low triggering voltages in both SCRs can be readily achieved without involving device or junction breakdown.",

author = "Chung-Yu Wu and Ming-Dou Ker and Lee, {Chung Yuan} and Joe Ko and Larry Lin",

year = "1991",

month = dec,

day = "1",

doi = "10.1109/CICC.1991.164085",

language = "English",

isbn = "0780300157",

series = "Proceedings of the Custom Integrated Circuits Conference",

publisher = "Publ by IEEE",

booktitle = "Proceedings of the Custom Integrated Circuits Conference",

note = "Proceedings of the IEEE 1991 Custom Integrated Circuits Conference ; Conference date: 12-05-1991 Through 15-05-1991",

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Wu, C-Y, Ker, M-D, Lee, CY, Ko, J & Lin, L 1991, A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI. 於 Proceedings of the Custom Integrated Circuits Conference. Proceedings of the Custom Integrated Circuits Conference, Publ by IEEE, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference, San Diego, CA, USA, 12/05/91. https://doi.org/10.1109/CICC.1991.164085

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T1 - A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI

AU - Wu, Chung-Yu

AU - Ker, Ming-Dou

AU - Lee, Chung Yuan

AU - Ko, Joe

AU - Lin, Larry

PY - 1991/12/1

Y1 - 1991/12/1

N2 - A novel CMOS on-chip ESD (electrostatic discharge) protection circuit which consists of dual parasitic SCR structures is proposed. Experimental results show that it can successfully provide for negative and positive ESD protection with failure thresholds greater than ±1 kV and ±10 kV in machine-mode (MM) and human-body-mode (HBM) testing, respectively. Moreover, low triggering voltages in both SCRs can be readily achieved without involving device or junction breakdown.

AB - A novel CMOS on-chip ESD (electrostatic discharge) protection circuit which consists of dual parasitic SCR structures is proposed. Experimental results show that it can successfully provide for negative and positive ESD protection with failure thresholds greater than ±1 kV and ±10 kV in machine-mode (MM) and human-body-mode (HBM) testing, respectively. Moreover, low triggering voltages in both SCRs can be readily achieved without involving device or junction breakdown.

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U2 - 10.1109/CICC.1991.164085

DO - 10.1109/CICC.1991.164085

M3 - Conference contribution

AN - SCOPUS:0026392746

SN - 0780300157

T3 - Proceedings of the Custom Integrated Circuits Conference

BT - Proceedings of the Custom Integrated Circuits Conference

PB - Publ by IEEE

T2 - Proceedings of the IEEE 1991 Custom Integrated Circuits Conference

Y2 - 12 May 1991 through 15 May 1991

ER -

A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI

摘要

出版系列

Conference

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引用此