A new five-mask-count process for fabrication of pol y-si nanowire-channel cmos inverters

Chia Hao Kuo, Horng Chih Lin*, Tiao Yuan Huang

*此作品的通信作者

    研究成果: Conference article同行評審

    摘要

    A new five-mask-count process for fabricating CMOS inverters with poly-Si NW channels is demonstrated. The fabricated devices show reasonable symmetric driving current by well-designed structural parameters. From voltage transfer characteristics (VTC), an abrupt transition, large noise margins, and high voltage gain are obtained with a supply voltage of 5V.

    原文English
    頁(從 - 到)1086-1089
    頁數4
    期刊Digest of Technical Papers - SID International Symposium
    43
    發行號1
    DOIs
    出版狀態Published - 2012
    事件49th SID International Symposium, Seminar and Exhibition, dubbed Display Week, 2012 - Boston, United States
    持續時間: 3 6月 20128 6月 2012

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