TY - JOUR
T1 - A new five-mask-count process for fabrication of pol y-si nanowire-channel cmos inverters
AU - Kuo, Chia Hao
AU - Lin, Horng Chih
AU - Huang, Tiao Yuan
N1 - Publisher Copyright:
© 2012 SID.
PY - 2012
Y1 - 2012
N2 - A new five-mask-count process for fabricating CMOS inverters with poly-Si NW channels is demonstrated. The fabricated devices show reasonable symmetric driving current by well-designed structural parameters. From voltage transfer characteristics (VTC), an abrupt transition, large noise margins, and high voltage gain are obtained with a supply voltage of 5V.
AB - A new five-mask-count process for fabricating CMOS inverters with poly-Si NW channels is demonstrated. The fabricated devices show reasonable symmetric driving current by well-designed structural parameters. From voltage transfer characteristics (VTC), an abrupt transition, large noise margins, and high voltage gain are obtained with a supply voltage of 5V.
UR - http://www.scopus.com/inward/record.url?scp=85075652194&partnerID=8YFLogxK
U2 - 10.1002/j.2168-0159.2012.tb05980.x
DO - 10.1002/j.2168-0159.2012.tb05980.x
M3 - Conference article
AN - SCOPUS:85075652194
SN - 0097-966X
VL - 43
SP - 1086
EP - 1089
JO - Digest of Technical Papers - SID International Symposium
JF - Digest of Technical Papers - SID International Symposium
IS - 1
T2 - 49th SID International Symposium, Seminar and Exhibition, dubbed Display Week, 2012
Y2 - 3 June 2012 through 8 June 2012
ER -