A new failure mechanism on analog I/O cell under ND-mode ESD stress in deep-submicron CMOS technology

Shih Hung Chen; Ming-Dou Ker; Che Hao Chuang

doi:10.1109/IPFA.2005.1469163

A new failure mechanism on analog I/O cell under ND-mode ESD stress in deep-submicron CMOS technology

Shih Hung Chen^*, Ming-Dou Ker, Che Hao Chuang

^*此作品的通信作者

研究成果: Paper › 同行評審

1 引文斯高帕斯（Scopus）

摘要

A new ESD failure mechanism has been found in the analog pins with pure-diode protection scheme during ND-mode ESD stress. The failure is caused by the parasitic npn interaction between ESD protection diode and guard ring structure. The parasitic npn bipolar, which was constructed between the N+/PW diode and the N+/NW guard ring, provides the discharging path between the I/O pad to the grounded VDD under the ND-mode ESD stress to cause a low ESD robustness of the analog I/O cell. The solution to overcome this ESD failure is also proposed.

原文	English
頁面	209-212
頁數	4
DOIs	https://doi.org/10.1109/IPFA.2005.1469163
出版狀態	Published - 6月 2005
事件	12th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2005 - Singapore, 新加坡持續時間: 27 6月 2005 → 1 7月 2005

Conference

Conference	12th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2005
國家/地區	新加坡
城市	Singapore
期間	27/06/05 → 1/07/05

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10.1109/IPFA.2005.1469163

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title = "A new failure mechanism on analog I/O cell under ND-mode ESD stress in deep-submicron CMOS technology",

abstract = "A new ESD failure mechanism has been found in the analog pins with pure-diode protection scheme during ND-mode ESD stress. The failure is caused by the parasitic npn interaction between ESD protection diode and guard ring structure. The parasitic npn bipolar, which was constructed between the N+/PW diode and the N+/NW guard ring, provides the discharging path between the I/O pad to the grounded VDD under the ND-mode ESD stress to cause a low ESD robustness of the analog I/O cell. The solution to overcome this ESD failure is also proposed.",

author = "Chen, {Shih Hung} and Ming-Dou Ker and Chuang, {Che Hao}",

year = "2005",

month = jun,

doi = "10.1109/IPFA.2005.1469163",

language = "English",

pages = "209--212",

note = "12th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2005 ; Conference date: 27-06-2005 Through 01-07-2005",

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T1 - A new failure mechanism on analog I/O cell under ND-mode ESD stress in deep-submicron CMOS technology

AU - Chen, Shih Hung

AU - Ker, Ming-Dou

AU - Chuang, Che Hao

PY - 2005/6

Y1 - 2005/6

N2 - A new ESD failure mechanism has been found in the analog pins with pure-diode protection scheme during ND-mode ESD stress. The failure is caused by the parasitic npn interaction between ESD protection diode and guard ring structure. The parasitic npn bipolar, which was constructed between the N+/PW diode and the N+/NW guard ring, provides the discharging path between the I/O pad to the grounded VDD under the ND-mode ESD stress to cause a low ESD robustness of the analog I/O cell. The solution to overcome this ESD failure is also proposed.

AB - A new ESD failure mechanism has been found in the analog pins with pure-diode protection scheme during ND-mode ESD stress. The failure is caused by the parasitic npn interaction between ESD protection diode and guard ring structure. The parasitic npn bipolar, which was constructed between the N+/PW diode and the N+/NW guard ring, provides the discharging path between the I/O pad to the grounded VDD under the ND-mode ESD stress to cause a low ESD robustness of the analog I/O cell. The solution to overcome this ESD failure is also proposed.

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U2 - 10.1109/IPFA.2005.1469163

DO - 10.1109/IPFA.2005.1469163

M3 - Paper

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T2 - 12th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2005

Y2 - 27 June 2005 through 1 July 2005

ER -

A new failure mechanism on analog I/O cell under ND-mode ESD stress in deep-submicron CMOS technology

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