A new failure mechanism on analog I/O cell under ND-mode ESD stress in deep-submicron CMOS technology

Shih Hung Chen*, Ming-Dou Ker, Che Hao Chuang

*此作品的通信作者

    研究成果: Paper同行評審

    1 引文 斯高帕斯(Scopus)

    摘要

    A new ESD failure mechanism has been found in the analog pins with pure-diode protection scheme during ND-mode ESD stress. The failure is caused by the parasitic npn interaction between ESD protection diode and guard ring structure. The parasitic npn bipolar, which was constructed between the N+/PW diode and the N+/NW guard ring, provides the discharging path between the I/O pad to the grounded VDD under the ND-mode ESD stress to cause a low ESD robustness of the analog I/O cell. The solution to overcome this ESD failure is also proposed.

    原文English
    頁面209-212
    頁數4
    DOIs
    出版狀態Published - 6月 2005
    事件12th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2005 - Singapore, Singapore
    持續時間: 27 6月 20051 7月 2005

    Conference

    Conference12th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2005
    國家/地區Singapore
    城市Singapore
    期間27/06/051/07/05

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