A new dynamic scaling FFT processor

Yu Wei Lin*, Chen-Yi Lee

*此作品的通信作者

研究成果: Paper同行評審

摘要

A new FFT processor with radix-8 algorithm and novel matrix buffer is presented in this paper. About 64 K bit memory can be saved in 8 K-point FFT by new dynamic scaling approach. Moreover, with data scheduling and prefetched buffering, single-port memory can be adopted in our FFT processor. A test chip for 8 K mode DVB-T system has been designed and fabricated using 0.18 μm CMOS process with core area of 4.84mm2 and consumes only 25.2 mW at 20 MHz.

原文English
頁面449-452
頁數4
出版狀態Published - 1 十二月 2004
事件2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan
持續時間: 6 十二月 20049 十二月 2004

Conference

Conference2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
國家/地區Taiwan
城市Tainan
期間6/12/049/12/04

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