TY - JOUR
T1 - A new delta-sigma analog to digital converter with high-resolution and low offset for detecting photoplethysmography signal
AU - Pribadi, Eka Fitrah
AU - Pandey, Rajeev Kumar
AU - Chao, Paul C.P.
N1 - Publisher Copyright:
© 2022, The Author(s), under exclusive licence to Springer-Verlag GmbH Germany, part of Springer Nature.
PY - 2022/10
Y1 - 2022/10
N2 - A high-resolution, low offset delta-sigma analog to digital converter is presented for detecting photoplethysmography (PPG) signals, which oscillates in 1/f noise frequency band between 0.1 and 10 Hz. A delta-sigma analog-to-digital converter (DS ADC) is choosen for PPG application because it has wide dynamic range, high-resolution, and can be integrated with chopper-based operational amplifier. a chopper-based operational amplifier converts 1/f noise and dc offset to high-frequency noise, which acts as a virtual high-pass filter. Implementing a lowpass filter using a decimation filter can filter the high-frequency signal. Thus, the circuit becomes a new bandpass filter. A second-order continuous-time delta-sigma modulator is used in the DS ADC circuits. TSMC 180 nm technology was used to design and simulate the delta-sigma modulator circuits. The active area of the continuous-time delta-sigma modulator is 746 µm × 399 µm and was built using TSMC 180 nm technology. It has a bandwidth of 10 Hz and 512 oversampling ratios. The SFDR of the circuit is greater than 70 dB. The delta-sigma modulator consumes 35.61 µW of power. To ensure the circuitry works in a variety of scenarios, the simulation is run in three different types of corners, SS, TT, and FF, successfully validating the designed performance.
AB - A high-resolution, low offset delta-sigma analog to digital converter is presented for detecting photoplethysmography (PPG) signals, which oscillates in 1/f noise frequency band between 0.1 and 10 Hz. A delta-sigma analog-to-digital converter (DS ADC) is choosen for PPG application because it has wide dynamic range, high-resolution, and can be integrated with chopper-based operational amplifier. a chopper-based operational amplifier converts 1/f noise and dc offset to high-frequency noise, which acts as a virtual high-pass filter. Implementing a lowpass filter using a decimation filter can filter the high-frequency signal. Thus, the circuit becomes a new bandpass filter. A second-order continuous-time delta-sigma modulator is used in the DS ADC circuits. TSMC 180 nm technology was used to design and simulate the delta-sigma modulator circuits. The active area of the continuous-time delta-sigma modulator is 746 µm × 399 µm and was built using TSMC 180 nm technology. It has a bandwidth of 10 Hz and 512 oversampling ratios. The SFDR of the circuit is greater than 70 dB. The delta-sigma modulator consumes 35.61 µW of power. To ensure the circuitry works in a variety of scenarios, the simulation is run in three different types of corners, SS, TT, and FF, successfully validating the designed performance.
UR - http://www.scopus.com/inward/record.url?scp=85136476216&partnerID=8YFLogxK
U2 - 10.1007/s00542-022-05360-2
DO - 10.1007/s00542-022-05360-2
M3 - Article
AN - SCOPUS:85136476216
SN - 0946-7076
VL - 28
SP - 2369
EP - 2379
JO - Microsystem Technologies
JF - Microsystem Technologies
IS - 10
ER -