A New Criterion for Transient Latchup Analysis in Bulk CMOS

Yeu Haw Yang, Chung-Yu Wu

研究成果: Article同行評審

9 引文 斯高帕斯(Scopus)

摘要

This paper describes a new criterion for transient latchup of p-n-p-n structures initiated by current pulses. Based upon the circuit-oriented model, the terminal currents and voltages of the transistors as a function of the pulsed triggering currents are characterized, and the charge storage within p-n-p-n structures is investigated. It is found that, to maintain the regeneration process, the change of charge stored in junction depletion capacitances of a p-n-p-n structure must be greater than a certain value independent of the triggering currents. Thus, the new criterion is constructed in terms of the constant charge storage within a p-n-p-n structure. Applying the criterion, latchup immunity against pulsed triggering currents can be evaluated with respect to process and device parameters. Both SPICE simulations and experimental results confirm the validity of the proposed transient criterion. It is found that large transit time of bipolar transistors and large well-substrate junction depletion capacitance lead to higher latchup immunity against pulsed triggering currents.

原文English
頁(從 - 到)1336-1347
頁數12
期刊IEEE Transactions on Electron Devices
36
發行號7
DOIs
出版狀態Published - 1 一月 1989

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