A new analytical delay and noise model for on-chip RLC interconnect

Y. Cao; X. Huang; D. Sylvester; N. Chang; Chen-Ming Hu

doi:10.1109/IEDM.2000.904444

A new analytical delay and noise model for on-chip RLC interconnect

Y. Cao^*, X. Huang, D. Sylvester, N. Chang, Chen-Ming Hu

^*此作品的通信作者

國際半導體產業學院

研究成果: Conference article › 同行評審

20 引文斯高帕斯（Scopus）

摘要

In this paper, we develop a 2^nd order distributed RLC waveform model that captures both delay and overshoot effects more accurately than previous 1^st order models. We then present a new approach to decoupling a set of coupled RLC lines by examining current return paths. Noise and delay results from this technique match SPICE for a wide range of input parameters.

原文	English
頁（從 - 到）	823-826
頁數	4
期刊	Technical Digest - International Electron Devices Meeting
DOIs	https://doi.org/10.1109/IEDM.2000.904444
出版狀態	Published - 1 12月 2000
事件	2000 IEEE International Electron Devices Meeting - San Francisco, CA, 美國持續時間: 10 12月 2000 → 13 12月 2000

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10.1109/IEDM.2000.904444

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abstract = "In this paper, we develop a 2nd order distributed RLC waveform model that captures both delay and overshoot effects more accurately than previous 1st order models. We then present a new approach to decoupling a set of coupled RLC lines by examining current return paths. Noise and delay results from this technique match SPICE for a wide range of input parameters.",

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AU - Huang, X.

AU - Sylvester, D.

AU - Chang, N.

AU - Hu, Chen-Ming

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AB - In this paper, we develop a 2nd order distributed RLC waveform model that captures both delay and overshoot effects more accurately than previous 1st order models. We then present a new approach to decoupling a set of coupled RLC lines by examining current return paths. Noise and delay results from this technique match SPICE for a wide range of input parameters.

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JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

T2 - 2000 IEEE International Electron Devices Meeting

Y2 - 10 December 2000 through 13 December 2000

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A new analytical delay and noise model for on-chip RLC interconnect

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