A new 2-D 8×8 DCT/IDCT core design using group distributed arithmetic

Jiun-In  Guo*, Jia Wei Chen, Han Chen Chen

*此作品的通信作者

研究成果: Conference article同行評審

5 引文 斯高帕斯(Scopus)

摘要

This paper presents a new two-dimensional (2-D) 8×8 discrete cosine/inverse discrete cosine transform (DCT/IDCT) core design using the group distributed arithmetic (GDA) approach. We adopt the way of DA computation and exploit the good features of the cyclic convolution to facilitate an efficient realization of 2-D 8×8 DCT/IDCT core design using shared ROM modules, barrier shifters, and accumulators. To increase the ROM utilization, we re-arrange the content of ROM into several groups in which all the elements in a group will be accessed simultaneously in accumulating the DCT/IDCT outputs. The comparison results with the existing designs show that the proposed design possesses averagely 62.6 % reduction in the delay-area products (ns*Kμm2) based on a 0.35μm CMOS technology.

原文English
期刊Proceedings - IEEE International Symposium on Circuits and Systems
2
DOIs
出版狀態Published - 14 7月 2003
事件Proceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand
持續時間: 25 5月 200328 5月 2003

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