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A near-threshold cell-based all-digital PLL with hierarchical band-selection G-DCO for fast lock-in and low-power applications
Chia Wen Chang, Yuan Hua Chu,
Shyh-Jye Jou
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引文 斯高帕斯（Scopus）
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Keyphrases
Low Power Applications
100%
Fast Lock
100%
Cell-based
100%
Band Selection
100%
All-digital Phase-locked Loop (ADPLL)
100%
Near-threshold
100%
Clock Frequency
33%
Dynamic Voltage Frequency Scaling
33%
Wide Frequency Range
33%
Output Frequency
16%
Low Power
16%
Low Voltage
16%
Power Consumption
16%
Low-voltage Operation
16%
Digitally Controlled Oscillator
16%
Low Jitter
16%
Frequency Acquisition
16%
Frequency Resolution
16%
Near-threshold Region
16%
Period Jitter
16%
Frequency Estimation Algorithm
16%
Jitter Performance
16%
Scaled Systems
16%
Computer Science
Phase Locked Loop
100%
Band Selection
100%
Clock Frequency
33%
Dynamic Voltage
33%
Supply Voltage
16%
Power Consumption
16%
Estimation Algorithm
16%
Frequency Resolution
16%
Output Frequency
16%
Threshold Region
16%
Frequency Estimation
16%
Engineering
Phase Locked Loop
100%
Clock Frequency
33%
Time Domain
16%
Supply Voltage
16%
Electric Power Utilization
16%
Output Frequency
16%
Frequency Estimation
16%
Frequency Resolution
16%
Oscillator
16%