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A multicycle communication architecture and synthesis flow for global interconnect resource sharing
Wei Sheng Huang
*
, Yu Ru Hong,
Juinn-Dar Huang
, Ya Shih Huang
*
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引文 斯高帕斯(Scopus)
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Keyphrases
Resource Sharing
100%
Communication Architecture
100%
Synthesis Flow
100%
Global Interconnect
100%
Interconnect Resources
100%
Multicycle Communication
100%
Communication Synthesis
100%
Global Resources
75%
Distributed Register
75%
Integer Linear Programming
50%
Distributed-register Architecture
50%
Scheduling Problem
25%
Latency
25%
Allocation Problem
25%
Deep Submicron Technology
25%
Channel Allocation
25%
Data Transfer
25%
Architectural Synthesis
25%
Register Allocation
25%
Path Scheduling
25%
Wire Delay
25%
System Latency
25%
Computer Science
Resource Sharing
100%
Interconnect Resource
100%
Communication Architecture
100%
Global Resource
75%
Integer-Linear Programming
50%
Architecture Register
50%
Scheduling Problem
25%
Experimental Result
25%
Allocation Problem
25%
Architectural Synthesis
25%
Register Allocation
25%