A Multi-Step Incremental Analog-to-Digital Converter with a Single Opamp and Two- Capacitor SAR Extended Counting

Shih Che Kuo, Jia Sheng Huang, Yu Cheng Huang, Chia Wei Kao, Che Wei Hsu, Chia Hung Chen*

*此作品的通信作者

研究成果: Article同行評審

1 引文 斯高帕斯(Scopus)

摘要

This work describes a hybrid incremental ADC (IADC) with two-capacitor (2-C) successive-approximation registers (SAR) extended counting in two-step operation to achieve high resolution data conversion. The circuits in the first step is acting as a first-order incremental analog-to-digital converter (IADC). Finite impulse response (FIR) DAC is incorporated in the loop filter to reduce the transient voltage step. It is reconfigured as a 2-C SAR to perform extended counting technique in the second step. Only one opamp is re-used in both steps. The hardware is prototyped in 0.18~mu textm CMOS technology, and the hybrid ADC accomplishes a measured DR / SNR / SNDR of 100.2 / 97.1 / 96.6 dB and an input signal bandwidth of 1.2 kHz. Operated at 1.5-V, it consumes 33.2~mu textW , and this achieves a Walden figure-of-merit (FoM) of 0.25 pJ/conversion-step and Schreier FoM of 175.8 dB.

原文English
文章編號9431347
頁(從 - 到)2890-2899
頁數10
期刊IEEE Transactions on Circuits and Systems I: Regular Papers
68
發行號7
DOIs
出版狀態Published - 7月 2021

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