A monolithic CMOS MEMS accelerometer with chopper correlated double sampling readout circuit

Chun Kai Wang*, Che Sheng Chen, Kuei-Ann Wen

*此作品的通信作者

    研究成果: Conference contribution同行評審

    16 引文 斯高帕斯(Scopus)

    摘要

    A monolithic CMOS MEMS capacitive accelerometer with micropower analog readout circuit is presented in this paper. In order to optimize noise-power performance of accelerometer in limited area, a specification driven MEMS/IC co-design flow is adopted. In analog readout circuit design, the proposed circuit architecture combines chopper stabilization and correlated double sampling to suppress low frequency noise and compensate DC offset. The RMS input referred noise voltage is 9.82 nV/Hz under 100Hz. The power consumption is 36uW at 100kHz modulation frequency.

    原文English
    主出版物標題2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
    頁面2023-2026
    頁數4
    DOIs
    出版狀態Published - 2 8月 2011
    事件2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 - Rio de Janeiro, Brazil
    持續時間: 15 5月 201118 5月 2011

    出版系列

    名字Proceedings - IEEE International Symposium on Circuits and Systems
    ISSN(列印)0271-4310

    Conference

    Conference2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
    國家/地區Brazil
    城市Rio de Janeiro
    期間15/05/1118/05/11

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