A module generator for parameterized DSP core

Ya Lan Tsao*, Yu Chun Lin, Wei Hao Chen, Bo Shiang Huang, Shyh-Jye Jou

*此作品的通信作者

    研究成果同行評審

    1 引文 斯高帕斯(Scopus)

    摘要

    In this paper, a parameterized module generator of DSP core for embedded application is proposed. Some special functions for the communication applications are included in this DSP core. Moreover, key parameters of the DSP core are identified and analyzed to show their effects on performance index such as execution cycle, hardware gate count and power consumption. The parameters of the DSP core and the special functions required can be specified by user which is required by the application. The DSP core which generated by the generator is synthesizable and flexible RTL code for system integration. The turn around time of design process can be dramatically decreased. Furthermore, the generator can automatically optimize the structure of DSP core for different parameters. The design examples show that the variety of selection in implementation by using this parameterized generator and its flow provides the system designer to obtain better result in area, speed and power trade-off.

    原文English
    頁面361-364
    頁數4
    DOIs
    出版狀態Published - 12月 2004
    事件2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, 台灣
    持續時間: 6 12月 20049 12月 2004

    Conference

    Conference2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
    國家/地區台灣
    城市Tainan
    期間6/12/049/12/04

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