A Model-Based-Random-Forest Framework for Predicting Vt Mean and Variance Based on Parallel Id Measurement

Chien Hsueh Lin*, Chih Ying Tsai, Kao Chi Lee, Sung Chu Yu, Wen Rong Liau, Alex Chun Liang Hou, Ying Yen Chen, Chun Yi Kuo, Jih Nung Lee, Chia-Tso Chao

*此作品的通信作者

研究成果: Article同行評審

2 引文 斯高帕斯(Scopus)

摘要

To measure the variation of device Vt requires long test for conventional wafer acceptance test (WAT) test structures. This paper presents a framework that can efficiently and effectively obtain the mean and variance of Vt for a large number of designs under test (DUTs). The proposed framework applies the model-based random forest as its core model-fitting technique to learn a model that can predict the mean and variance of Vt based only on the combined Id measured from parallel connected DUTs. The proposed framework can further minimize the total number of Id measurement required for prediction models while limiting their accuracy loss. The experimental results based on the SPICE simulation of a UMC 28-nm technology demonstrate that the proposed model-fitting framework can achieve a more than 99% R-squared for predicting either Vt mean or Vt variance. Compared to conventional WAT test structures using binary search, our proposed framework can achieve a 120.3 × speedup on overall test time for test structures with 800 DUTs.

原文English
文章編號8194921
頁(從 - 到)2139-2151
頁數13
期刊IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
37
發行號10
DOIs
出版狀態Published - 1 10月 2018

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