In this paper, we introduce a 10 Gbps digital baseband transceiver with 1V supply voltage, 16-QAM, 3/4 code rate single carrier mode using 28 nm CMOS process to do the implementation. In millimeter wave communications, well-defined standard, IEEE 802.11ad is referenced for our system design and simulation. We target at modified chip rate 2.5 GHz with 4 times parallelism hardware at clock rate 625 MHz. The overall transceiver architecture design with hardware implementation considerations will be proposed. With the smart shared memory allocation, we can reduce 31% of the total amount. According to the referenced specifications, we achieve the required bit error rate 3 × 10-7 before SNR 18.5 dB. After the system algorithm design, we implement the hardware with the core area 2.92 mm2 with measured power 1.8 Watt for baseband transceiver chip. The performance of energy per bit is 0.023 nJ and 0.211 nJ per bit for Tx and Rx, including ADC/DAC.